From b476a41c92a4aabf01af5996308ba29abdf30eb6 Mon Sep 17 00:00:00 2001 From: "Morgan 'ARR\\!' Allen" Date: Thu, 2 Dec 2021 10:00:57 -0800 Subject: [PATCH] add more dio pins to lora_cfg, channels, (en/dis)able methods for FHSS --- include/esp32-lora.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/include/esp32-lora.h b/include/esp32-lora.h index 20f0b23..10df267 100644 --- a/include/esp32-lora.h +++ b/include/esp32-lora.h @@ -107,19 +107,25 @@ typedef struct lora32_cfg_t { uint8_t cipo; uint8_t copi; uint8_t clk; - uint8_t dio0; uint8_t reset; uint8_t fifoIdx; - - long frequency; + uint8_t channel; uint8_t bandwidth; - uint8_t spreadingFactor; uint8_t codingRate; + + int8_t dio0; + int8_t dio1; + int8_t dio2; + int8_t channels[64]; + + long frequency; + uint16_t preamble; bool useCRC; bool implicitHeader; + bool enableFHSS; receiveCallback receive; txdoneCallback tx_done; @@ -138,9 +144,11 @@ uint8_t lora32_data_available(lora32_cfg_t *lora); double lora32_calc_datarate(lora32_cfg_t *lora); void lora32_dump_regs(lora32_cfg_t *lora); +void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period); void lora32_enable_continuous_rx(lora32_cfg_t *lora); void lora32_enable_single_rx(lora32_cfg_t *lora); void lora32_enable_cad(lora32_cfg_t *lora); +void lora32_disable_fhss(lora32_cfg_t *lora); void lora32_toggle_reset(lora32_cfg_t *lora); void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len); void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw);