From 1396434448869bcd361fe2623c8ac19d030895d4 Mon Sep 17 00:00:00 2001 From: "Morgan 'ARR\\!' Allen" Date: Thu, 2 Dec 2021 09:59:44 -0800 Subject: [PATCH 1/5] add register for FHSS --- include/esp32-lora.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/esp32-lora.h b/include/esp32-lora.h index 0037b06..20f0b23 100644 --- a/include/esp32-lora.h +++ b/include/esp32-lora.h @@ -29,6 +29,7 @@ #define REG_PREAMBLE_MSB 0x20 #define REG_PREAMBLE_LSB 0x21 #define REG_PAYLOAD_LENGTH 0x22 +#define REG_HOP_PERIOD 0x24 #define REG_MODEM_CONFIG_3 0x26 #define REG_RSSI_WIDEBAND 0x2c #define REG_DETECTION_OPTIMIZE 0x31 From b476a41c92a4aabf01af5996308ba29abdf30eb6 Mon Sep 17 00:00:00 2001 From: "Morgan 'ARR\\!' Allen" Date: Thu, 2 Dec 2021 10:00:57 -0800 Subject: [PATCH 2/5] add more dio pins to lora_cfg, channels, (en/dis)able methods for FHSS --- include/esp32-lora.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/include/esp32-lora.h b/include/esp32-lora.h index 20f0b23..10df267 100644 --- a/include/esp32-lora.h +++ b/include/esp32-lora.h @@ -107,19 +107,25 @@ typedef struct lora32_cfg_t { uint8_t cipo; uint8_t copi; uint8_t clk; - uint8_t dio0; uint8_t reset; uint8_t fifoIdx; - - long frequency; + uint8_t channel; uint8_t bandwidth; - uint8_t spreadingFactor; uint8_t codingRate; + + int8_t dio0; + int8_t dio1; + int8_t dio2; + int8_t channels[64]; + + long frequency; + uint16_t preamble; bool useCRC; bool implicitHeader; + bool enableFHSS; receiveCallback receive; txdoneCallback tx_done; @@ -138,9 +144,11 @@ uint8_t lora32_data_available(lora32_cfg_t *lora); double lora32_calc_datarate(lora32_cfg_t *lora); void lora32_dump_regs(lora32_cfg_t *lora); +void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period); void lora32_enable_continuous_rx(lora32_cfg_t *lora); void lora32_enable_single_rx(lora32_cfg_t *lora); void lora32_enable_cad(lora32_cfg_t *lora); +void lora32_disable_fhss(lora32_cfg_t *lora); void lora32_toggle_reset(lora32_cfg_t *lora); void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len); void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw); From 6ad9cba796bc3f7b199bac4fab987716cfef2786 Mon Sep 17 00:00:00 2001 From: "Morgan 'ARR\\!' Allen" Date: Thu, 2 Dec 2021 10:01:37 -0800 Subject: [PATCH 3/5] add primary enable/disable functions for FHSS --- main/esp32-lora.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/main/esp32-lora.c b/main/esp32-lora.c index eb46995..715cee5 100644 --- a/main/esp32-lora.c +++ b/main/esp32-lora.c @@ -107,6 +107,18 @@ void lora32_sleep(lora32_cfg_t *lora) { lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP); } +void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period) { + lora->enableFHSS = true; + + lora32_write_reg(lora, REG_HOP_PERIOD, period); +} + +void lora32_disable_fhss(lora32_cfg_t *lora) { + lora->enableFHSS = false; + + lora32_write_reg(lora, REG_HOP_PERIOD, 0); +} + void lora32_enable_tx(lora32_cfg_t *lora) { lora32_standby(lora); From a347f418c8e7be2f18b2e80b2896ee20521194d4 Mon Sep 17 00:00:00 2001 From: "Morgan 'ARR\\!' Allen" Date: Thu, 2 Dec 2021 10:02:08 -0800 Subject: [PATCH 4/5] add FHSS IRQ handling --- main/esp32-lora.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/main/esp32-lora.c b/main/esp32-lora.c index 715cee5..9bc0d2b 100644 --- a/main/esp32-lora.c +++ b/main/esp32-lora.c @@ -417,6 +417,21 @@ static void IRAM_ATTR lora32_dio_task(void *arg) { // these *should* fire at the same time, defaults to false if(lora->cad_done != NULL) lora->cad_done(lora, cad_detected); } + + if((irqs & IRQ_FHSS_CHANGE) == IRQ_FHSS_CHANGE) { + ESP_LOGI(TAG, "switching channel %d: %d", lora->channel, lora->channels[lora->channel]); + + if(lora->channel == 0 && lora->channels[lora->channel] == 0) continue; + + if(lora->channels[lora->channel] == 0) { + ESP_LOGI(TAG, "reseting to channel 0"); + lora->channel = 0; + } + + lora32_set_frequency(lora, lora->frequency + (lora->channels[lora->channel] * bandwidths[lora->bandwidth])); + + lora->channel++; + } } } From c5dc9c961df3356fb01371cffa2e0cd75f3bfa29 Mon Sep 17 00:00:00 2001 From: "Morgan 'ARR\\!' Allen" Date: Thu, 2 Dec 2021 10:03:05 -0800 Subject: [PATCH 5/5] add new dio handlers, consolidate DIO handlers to single function --- main/esp32-lora.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/main/esp32-lora.c b/main/esp32-lora.c index 9bc0d2b..de5a936 100644 --- a/main/esp32-lora.c +++ b/main/esp32-lora.c @@ -446,7 +446,7 @@ void lora32_read_data(lora32_cfg_t *lora, uint8_t *data) { } } -static void IRAM_ATTR lora32_on_dio0(void *arg) { +static void IRAM_ATTR lora32_on_dio(void *arg) { xQueueSend(dio_event_queue, arg, (TickType_t)0); } @@ -551,14 +551,18 @@ uint8_t lora32_init(lora32_cfg_t *lora) { if(lora->receive != NULL) { ESP_LOGI(TAG, "Setting GPIO Interrupt"); + // TODO check at least one DIOx pin is not NULL + io_conf.intr_type = GPIO_PIN_INTR_POSEDGE; - io_conf.pin_bit_mask = (1ULL << lora->dio0); + io_conf.pin_bit_mask = ((1ULL << lora->dio0) | (1ULL << lora->dio1) | (1ULL << lora->dio2)); io_conf.mode = GPIO_MODE_INPUT; io_conf.pull_down_en = 0; io_conf.pull_up_en = 0; gpio_config(&io_conf); gpio_set_intr_type(lora->dio0, GPIO_INTR_POSEDGE); + gpio_set_intr_type(lora->dio1, GPIO_INTR_POSEDGE); + gpio_set_intr_type(lora->dio2, GPIO_INTR_POSEDGE); // the DIO interrupt handling for every device is done from one task if(dio_task_handle == NULL) { @@ -575,7 +579,14 @@ uint8_t lora32_init(lora32_cfg_t *lora) { // add ISR handler to the global service started (once) above ESP_LOGI(TAG, "Installing ISR handler for GPIO%d", lora->dio0); - gpio_isr_handler_add(lora->dio0, lora32_on_dio0, lora); + if(lora->dio0 > -1) + gpio_isr_handler_add(lora->dio0, lora32_on_dio, (void*)lora); + + if(lora->dio1 > -1) + gpio_isr_handler_add(lora->dio1, lora32_on_dio, (void*)lora); + + if(lora->dio2 > -1) + gpio_isr_handler_add(lora->dio2, lora32_on_dio, (void*)lora); } return 1;