#ifndef _LORA32_H__
#define _LORA32_H__

#include "driver/spi_common.h"
#include "driver/spi_master.h"
#include "freertos/event_groups.h"

#define REG_FIFO                 0x00
#define REG_OP_MODE              0x01
#define REG_BR_MSB               0x02
#define REG_BR_LSB               0x03
#define REG_FD_MSB               0x04
#define REG_FD_LSB               0x05
#define REG_FRF_MSB              0x06
#define REG_FRF_MID              0x07
#define REG_FRF_LSB              0x08
#define REG_PA_CONFIG            0x09
#define REG_LNA                  0x0c
#define REG_FIFO_ADDR_PTR        0x0d
#define REG_FIFO_TX_BASE_ADDR    0x0e
#define REG_FIFO_RX_BASE_ADDR    0x0f
#define REG_FIFO_RX_CURRENT_ADDR 0x10
#define REG_IRQ_FLAGS            0x12
#define REG_RX_NB_BYTES          0x13
#define REG_MODEM_STATUS         0x18
#define REG_PKT_RSSI_VALUE       0x1a
#define REG_RSSI_VALUE           0x1b
#define REG_MODEM_CONFIG_1       0x1d
#define REG_MODEM_CONFIG_2       0x1e
#define REG_PREAMBLE_MSB         0x20
#define REG_PREAMBLE_LSB         0x21
#define REG_PAYLOAD_LENGTH       0x22
#define REG_HOP_PERIOD           0x24
#define REG_MODEM_CONFIG_3       0x26
#define REG_RSSI_WIDEBAND        0x2c
#define REG_DETECTION_OPTIMIZE   0x31
#define REG_DETECTION_THRESHOLD  0x37
#define REG_SYNC_WORD            0x39
#define REG_DIO_MAPPING_1        0x40
#define REG_DIO_MAPPING_2        0x41
#define REG_VERSION              0x42
#define REG_PA_DAC               0x4D

// modes
#define MODE_SLEEP               0x00
#define MODE_STANDBY             0x01
#define MODE_TX                  0x03
#define MODE_RX_CONTINUOUS       0x05
#define MODE_RX_SINGLE           0x06
#define MODE_CAD_DETECT          0x07
#define MODE_LONG_RANGE_MODE     0x80

// PA config
#define PA_BOOST                 0x80

// IRQ masks
#define IRQ_RX_TIMEOUT             0x80
#define IRQ_RX_DONE                0x40
#define IRQ_PAYLOAD_CRC_ERROR      0x20
#define IRQ_VALID_HEADER           0x10
#define IRQ_TX_DONE                0x08
#define IRQ_CAD_DONE               0x04
#define IRQ_FHSS_CHANGE            0x02
#define IRQ_CAD_DETECTED           0x01

#define MAX_PKT_LENGTH             255

#define DETECT_OPT_SF6             0xC5
#define DETECT_THRES_SF6           0x0C
#define DETECT_OPT_OTHER           0xC3
#define DETECT_THRES_OTHER         0x0A

#define DEFAULT_SF 7
#define DEFAULT_PREAMBLE 8
#define DEFAULT_CR 5

#define DIO0_MODE_SHIFT   6
#define DIO0_MODE_RXDONE  0b00
#define DIO0_MODE_TXDONE  0b01
#define DIO0_MODE_CADDON  0b10

#define DIO1_MODE_SHIFT   4
#define DIO1_MODE_RXTIME  0b00
#define DIO1_MODE_FHSSCC  0b01
#define DIO1_MODE_CADDET  0b10

#define DIO3_MODE_SHIFT   2
#define DIO3_MODE_CADDON  0b00
#define DIO3_MODE_HEADVA  0b01
#define DIO3_MODE_CRCERR  0b10

#define DIO4_MODE_CADDET  0b00
#define DIO4_MODE_PLLLOC  0b10
#define DIO4_MODE_SHIFT   6

#define DIO5_MODE_SHIFT   4

#define ERR_LOR_VERSION_MISMATCH (01)

#define LORA32_DEFAULT_CONFIG {\
  .bandwidth = 7,\
  .codingRate = 5,\
  .frequency = 915000000,\
  .spreadingFactor = 11,\
  .preamble = DEFAULT_PREAMBLE,\
  .implicitHeader = false,\
  .useCRC = false,\
  .fifoIdx = 0,\
  .copi = 23,\
  .cipo = 19,\
  .clk = 18,\
  .dio0 = -1,\
  .dio1 = -1,\
  .dio2 = -1,\
  .nss = -1,\
  .reset = -1,\
  .spi_host = 1,\
}

enum freq {
  F433, F866, F915
} lora32_freq;

typedef enum {
  B78, B104, B156, B208, B3125, B417, B625, B125, B250, B500
} bandwidth;

extern const long long frequencies[3];
extern const long bandwidths[10];

typedef struct lora32_cfg_t lora32_cfg_t;

typedef void (*receiveCallback)(lora32_cfg_t *lora, uint8_t size);
typedef void (*txdoneCallback)(lora32_cfg_t *lora);
typedef void (*cadDoneCallback)(lora32_cfg_t *lora, bool detected);
typedef void (*cadDetectedCallback)(lora32_cfg_t *lora);

typedef struct {
  EventGroupHandle_t events;
} lora32_handle_t;

typedef struct lora32_modem_status_t {
  unsigned int detected:1;
  unsigned int synced:1;
  unsigned int rx:1;
  unsigned int valid:1;
  unsigned int clear:1;
  unsigned int cr:3;
} lora32_modem_status_t;

typedef struct lora32_cfg_t {
  uint8_t fifoIdx;
  uint8_t channel;
  uint8_t bandwidth;
  uint8_t spreadingFactor;
  uint8_t codingRate;
  uint8_t version; // to be written on init by the driver

  int8_t nss;
  int8_t cipo;
  int8_t copi;
  int8_t clk;
  int8_t reset;
  int8_t dio0;
  int8_t dio1;
  int8_t dio2;
  int8_t channels[64];

  long frequency;

  uint16_t preamble;

  bool useCRC;
  bool implicitHeader;
  bool enableFHSS;

  receiveCallback receive;
  txdoneCallback tx_done;
  cadDoneCallback cad_done;
  cadDetectedCallback cad_detected;

  uint8_t spi_host;
  spi_device_handle_t spi;

  lora32_handle_t handle;
} lora32_cfg_t;

uint8_t lora32_spi_init(lora32_cfg_t *config);
uint8_t lora32_init(lora32_cfg_t *config);
uint8_t lora32_data_available(lora32_cfg_t *lora);
int16_t lora32_get_packet_rssi(lora32_cfg_t *lora);
int16_t lora32_get_rssi(lora32_cfg_t *lora);

double lora32_calc_datarate(lora32_cfg_t *lora);
void lora32_dump_regs(lora32_cfg_t *lora);
void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period);
void lora32_enable_continuous_rx(lora32_cfg_t *lora);
void lora32_enable_single_rx(lora32_cfg_t *lora);
void lora32_enable_cad(lora32_cfg_t *lora);
void lora32_disable_fhss(lora32_cfg_t *lora);
void lora32_toggle_reset(lora32_cfg_t *lora);
void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
void lora32_set_bandwidth(lora32_cfg_t *lora, bandwidth bw);
void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr);
void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora);
void lora32_read_data(lora32_cfg_t *lora, uint8_t *data);
void lora32_sleep(lora32_cfg_t *lora);
void lora32_standby(lora32_cfg_t *lora);

#endif // _LORA32_H__