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2021-06-16 10:09:24 -07:00
loranet2.pretty add 3d model for DORJI module 2021-06-16 10:08:59 -07:00
loranet2.kicad_pcb tweak pours to remove VCC from under all antenna pathways 2021-06-16 10:09:24 -07:00
loranet2.lib track symbol file 2021-06-15 16:42:36 -07:00
loranet2.pro simplified parts of design, switched to AP2112K-3.3 for power reg 2021-06-15 16:33:19 -07:00
loranet2.sch double checked pins, moved SPI to default pins 2021-06-15 17:43:11 -07:00