initial commit.... after 6 months
This commit is contained in:
Morgan Allen
commit
1906e8f46d
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@ -0,0 +1,25 @@
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menuconfig LORA32_ENABLED
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bool "LORA32"
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help
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Select this option to enable LORA32 driver and show the submodule with configuration
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config LORA32_NSS_PIN
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int "GPIO to handle NSS"
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depends on LORA32_ENABLED
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default 18
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help
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GPIO to handle NSS
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config LORA32_RESET_PIN
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int "GPIO to handle RESET"
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depends on LORA32_ENABLED
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default 14
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help
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GPIO to handle RESET
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config LORA32_DIO0_PIN
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int "GPIO to handle DIO0"
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depends on LORA32_ENABLED
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default 26
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help
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GPIO to handle DIO0
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@ -0,0 +1,8 @@
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#
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# This is a project Makefile. It is assumed the directory this Makefile resides in is a
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# project subdirectory.
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#
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PROJECT_NAME := esp32-lora
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include $(IDF_PATH)/make/project.mk
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# ESP32 LoRa (SX127*)
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Provides SPI driver for SX1276/SX1278 LoRa radio
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## Usage
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Designed to be used as `esp-idf component`. Suggested using as `git submodule`
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```
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git submodule add https://gitlab.com/morganrallen/esp32-lora.git components/esp32-lora/
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git submodule init
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git submodule update
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```
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## Configure
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Uses built in KConfig. Run `make menuconfig` and find config under `Component config` -> `LORA32`.
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Defaults targeted to TTGO LoRa OLED boards.
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ifdef CONFIG_LORA32_ENABLED
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COMPONENT_SRCDIRS := main
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COMPONENT_ADD_INCLUDEDIRS := main include
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COMPONENT_ADD_LDFLAGS := -lesp32-lora
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COMPONENT_EXTRA_CLEAN :=
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endif
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@ -0,0 +1,108 @@
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#ifndef _LORA32_H__
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#define _LORA32_H__
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#include "driver/spi_common.h"
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#include "driver/spi_master.h"
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#define REG_FIFO 0x00
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#define REG_OP_MODE 0x01
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#define REG_BR_MSB 0x02
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#define REG_BR_LSB 0x03
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#define REG_FD_MSB 0x04
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#define REG_FD_LSB 0x05
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#define REG_FRF_MSB 0x06
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#define REG_FRF_MID 0x07
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#define REG_FRF_LSB 0x08
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#define REG_PA_CONFIG 0x09
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#define REG_LNA 0x0c
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#define REG_FIFO_ADDR_PTR 0x0d
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#define REG_FIFO_TX_BASE_ADDR 0x0e
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#define REG_FIFO_RX_BASE_ADDR 0x0f
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#define REG_FIFO_RX_CURRENT_ADDR 0x10
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#define REG_IRQ_FLAGS 0x12
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#define REG_RX_NB_BYTES 0x13
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#define REG_PKT_RSSI_VALUE 0x1a
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#define REG_PKT_SNR_VALUE 0x1b
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#define REG_MODEM_CONFIG_1 0x1d
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#define REG_MODEM_CONFIG_2 0x1e
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#define REG_PREAMBLE_MSB 0x20
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#define REG_PREAMBLE_LSB 0x21
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_MODEM_CONFIG_3 0x26
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#define REG_RSSI_WIDEBAND 0x2c
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#define REG_DETECTION_OPTIMIZE 0x31
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#define REG_DETECTION_THRESHOLD 0x37
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#define REG_SYNC_WORD 0x39
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#define REG_DIO_MAPPING_1 0x40
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#define REG_VERSION 0x42
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// modes
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#define MODE_LONG_RANGE_MODE 0x80
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#define MODE_SLEEP 0x00
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#define MODE_STANDBY 0x01
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#define MODE_TX 0x03
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#define MODE_RX_CONTINUOUS 0x05
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#define MODE_RX_SINGLE 0x06
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// PA config
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#define PA_BOOST 0x80
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// IRQ masks
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#define IRQ_TX_DONE_MASK 0x08
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#define IRQ_PAYLOAD_CRC_ERROR_MASK 0x20
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#define IRQ_RX_DONE_MASK 0x40
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#define MAX_PKT_LENGTH 255
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#define DETECT_OPT_SF6 0xC5
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#define DETECT_OPT_OTHER 0xC3
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#define DETECT_THRES_SF6 0x0C
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#define DETECT_THRES_OTHER 0x0A
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#define DEFAULT_SF 7
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#define DEFAULT_PREAMBLE 8
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#define DEFAULT_CR 5
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enum freq {
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F433, F866, F915
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} lora32_freq;
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const long long frequencies[3];
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const long bandwidths[9];
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enum bandwidth {
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B78, B104, B156, B208, B3125, B417, B625, B125, B250
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};
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typedef void (*receiveCallback)(uint8_t *data, uint8_t size);
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typedef struct lora32_cfg_t {
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uint8_t nss;
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uint8_t dio0;
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uint8_t reset;
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uint8_t fifoIdx;
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long frequency;
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enum bandwidth bandwidth;
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uint8_t spreadingFactor;
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uint8_t codingRate;
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uint16_t preamble;
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bool useCRC;
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bool implicitHeader;
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bool poll_rx;
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receiveCallback receive;
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spi_device_handle_t spi;
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} lora32_cfg_t;
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lora32_cfg_t lora32_create();
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uint8_t lora32_init(lora32_cfg_t *config);
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uint8_t lora32_data_available(lora32_cfg_t *lora);
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uint8_t lora32_parse_packet(lora32_cfg_t *lora, uint8_t size);
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void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
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void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
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void lora32_dump_regs(lora32_cfg_t *lora);
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#endif // _LORA32_H__
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@ -0,0 +1,456 @@
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#include <string.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_log.h"
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#include "esp_heap_caps.h"
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#include "driver/gpio.h"
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#include "driver/spi_common.h"
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#include "driver/spi_master.h"
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#include "esp32-lora.h"
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#define READ_REG 0x7F
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#define WRITE_REG 0x80
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#define PIN_NUM_MISO 19
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#define PIN_NUM_MOSI 27
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#define PIN_NUM_CLK 5
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#define PA_OUTPUT_RFO_PIN 0
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#define PA_OUTPUT_PA_BOOST_PIN 1
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static xQueueHandle dio0_evt_queue = NULL;
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const long long frequencies[] = { 433e+6, 866e+6, 915e+6 };
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const long bandwidths[] = { 7.8e+3, 10.4e+3, 15.6e+3, 20.8e+3, 31.25e+3, 41.7e+3, 62.5e+3, 125e+3, 250e+3 };
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const char *TAG = "LoRa32";
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lora32_cfg_t lora32_create() {
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static spi_device_handle_t spi;
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return (lora32_cfg_t){
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.bandwidth = bandwidths[F866],
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.codingRate = DEFAULT_CR,
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.dio0 = CONFIG_LORA32_DIO0_PIN,
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.implicitHeader = false,
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.nss = CONFIG_LORA32_NSS_PIN,
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.reset = CONFIG_LORA32_RESET_PIN,
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.frequency = 866000000,
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.poll_rx = false,
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.preamble = DEFAULT_PREAMBLE,
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.spreadingFactor = DEFAULT_SF,
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.spi = spi,
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.receive = NULL,
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.useCRC = false,
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.fifoIdx = 0
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};
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}
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void lora32_send_cmd(lora32_cfg_t lora, uint8_t cmd, uint8_t value, uint8_t len, uint8_t *rx_buffer) {
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uint8_t tx_buffer[2];
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tx_buffer[0] = cmd;
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tx_buffer[1] = value;
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spi_transaction_t t;
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memset(&t, 0, sizeof(t));
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t.length = 8 * len;
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t.rxlength = 8 * len;
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t.tx_buffer = &tx_buffer;
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t.rx_buffer = rx_buffer;
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ESP_ERROR_CHECK(spi_device_transmit(lora.spi, &t));
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//ESP_LOGI(TAG, "send_cmd rx_data: 0x%2X 0x%2X", rx_buffer[0], rx_buffer[1]);
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}
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uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
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spi_transaction_t t;
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memset(&t, 0, sizeof(spi_transaction_t));
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t.length = 16;
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t.flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA;
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t.tx_data[0] = address & READ_REG;
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t.tx_data[1] = 0x00;
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ESP_ERROR_CHECK(spi_device_transmit(lora->spi, &t));
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//ESP_LOGI(TAG, "<%2X<%2X", address, t.rx_data[1]);
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return t.rx_data[1];
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}
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void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
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spi_device_handle_t spi = lora->spi;
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spi_transaction_t t;
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memset(&t, 0, sizeof(spi_transaction_t));
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//ESP_LOGI(TAG, ">%2X>%2X", address, value);
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t.length = 16;
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t.flags = SPI_TRANS_USE_TXDATA;
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t.tx_data[0] = address | WRITE_REG;
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t.tx_data[1] = value;
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ESP_ERROR_CHECK(spi_device_transmit(spi, &t));
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};
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void lora23_set_explicit_header(lora32_cfg_t *lora) {
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lora->implicitHeader = false;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE);
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}
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void lora23_set_implicit_header(lora32_cfg_t *lora) {
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lora->implicitHeader = true;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) | 0x01);
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}
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void lora32_idle(lora32_cfg_t *lora) {
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STANDBY);
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}
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void lora32_sleep(lora32_cfg_t *lora) {
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
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//ESP_LOGI(TAG, "REG_OP_MODE: 0x%2X", lora32_read_reg(spi, REG_OP_MODE));
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}
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void lora32_enable_tx(lora32_cfg_t *lora) {
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lora32_idle(lora);
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if(lora->implicitHeader)
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lora23_set_implicit_header(lora);
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else
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lora23_set_explicit_header(lora);
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// zero out receive buffer
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lora32_write_reg(lora, REG_FIFO_ADDR_PTR, 0);
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lora32_write_reg(lora, REG_PAYLOAD_LENGTH, 0);
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}
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void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
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lora32_enable_tx(lora);
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uint8_t i = 0;
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for(; (i < len && i < MAX_PKT_LENGTH); i++)
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lora32_write_reg(lora, REG_FIFO, data[i]);
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lora32_write_reg(lora, REG_PAYLOAD_LENGTH, len);
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
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ESP_LOGD(TAG, "lora32_send waiting for TX to finish");
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// can be made async by waiting for DIO0 and checking for IRQ_TX_DONE_MASK
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while((lora32_read_reg(lora, REG_IRQ_FLAGS) & IRQ_TX_DONE_MASK) == 0) {
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vTaskDelay(1 / portTICK_PERIOD_MS);
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}
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ESP_LOGD(TAG, "lora32_send TX done");
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lora32_write_reg(lora, REG_IRQ_FLAGS, IRQ_TX_DONE_MASK);
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}
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void lora32_set_frequency(lora32_cfg_t *lora, long frequency) {
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uint64_t frf = ((uint64_t)frequency << 19) / 32000000;
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ESP_LOGI(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
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ESP_LOGI(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
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ESP_LOGI(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
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lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16) & 0xFF);
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lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8) & 0xFF);
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lora32_write_reg(lora, REG_FRF_LSB, (uint8_t)(frf >> 0) & 0xFF);
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//ESP_LOGI(TAG, "REG_FRF_MSB: 0x%2X", lora32_read_reg(spi, REG_FRF_MSB));
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//ESP_LOGI(TAG, "REG_FRF_MID: 0x%2X", lora32_read_reg(spi, REG_FRF_MID));
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//ESP_LOGI(TAG, "REG_FRF_LSB: 0x%2X", lora32_read_reg(spi, REG_FRF_LSB));
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}
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void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
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ESP_LOGI(TAG, "set_tx_power(%d, %d)", level, output);
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if(output == PA_OUTPUT_RFO_PIN) {
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if(level > 14) level = 14;
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|
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lora32_write_reg(lora, REG_PA_CONFIG, 0x70 | level);
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} else {
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if(level < 2) level = 2;
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else if(level > 17) level = 17;
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|
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lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2));
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}
|
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//ESP_LOGI(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(spi, REG_PA_CONFIG));
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}
|
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uint8_t lora32_parse_packet(lora32_cfg_t *lora, uint8_t size) {
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uint8_t length = 0;
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uint8_t irqs = lora32_read_reg(lora, REG_IRQ_FLAGS);
|
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|
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if(size > 0) {
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lora23_set_implicit_header(lora);
|
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|
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lora32_write_reg(lora, REG_PAYLOAD_LENGTH, size & 0xFF);
|
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} else {
|
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lora23_set_explicit_header(lora);
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}
|
||||
|
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lora32_write_reg(lora, REG_IRQ_FLAGS, irqs);
|
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|
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//ESP_LOGI(TAG, "irqs: 0x%2X", irqs);
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//ESP_LOGI(TAG, "irqs: 0x%2X", lora32_read_reg(spi, REG_IRQ_FLAGS));
|
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|
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if ((irqs & IRQ_RX_DONE_MASK) && (irqs & IRQ_PAYLOAD_CRC_ERROR_MASK) == 0) {
|
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lora->fifoIdx = 0;
|
||||
|
||||
if(lora->implicitHeader) {
|
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length = lora32_read_reg(lora, REG_PAYLOAD_LENGTH);
|
||||
} else {
|
||||
length = lora32_read_reg(lora, REG_RX_NB_BYTES);
|
||||
}
|
||||
|
||||
lora32_write_reg(lora, REG_FIFO_ADDR_PTR, lora32_read_reg(lora, REG_FIFO_RX_CURRENT_ADDR));
|
||||
|
||||
lora32_idle(lora);
|
||||
} else if(lora32_read_reg(lora, REG_OP_MODE) != (MODE_LONG_RANGE_MODE | MODE_RX_SINGLE)) {
|
||||
lora32_write_reg(lora, REG_FIFO_ADDR_PTR, 0);
|
||||
//lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
|
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} else {
|
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//ESP_LOGI(TAG, "no irqs?");
|
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}
|
||||
|
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return length;
|
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}
|
||||
|
||||
uint8_t lora32_data_available(lora32_cfg_t *lora) {
|
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return lora32_read_reg(lora, REG_RX_NB_BYTES) - lora->fifoIdx;
|
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}
|
||||
|
||||
void lora32_poll_rx(void *vp) {
|
||||
lora32_cfg_t *lora = (lora32_cfg_t*)vp;
|
||||
uint8_t msg[MAX_PKT_LENGTH];
|
||||
|
||||
while(true) {
|
||||
lora32_parse_packet(lora, 0);
|
||||
|
||||
if(lora32_data_available(lora)) {
|
||||
memset(msg, 0, MAX_PKT_LENGTH);
|
||||
|
||||
while(lora32_data_available(lora)) {
|
||||
msg[lora->fifoIdx] = lora32_read_reg(lora, REG_FIFO);
|
||||
|
||||
lora->fifoIdx++;
|
||||
}
|
||||
|
||||
lora->receive((uint8_t*)&msg, lora->fifoIdx);
|
||||
}
|
||||
|
||||
vTaskDelay(100 / portTICK_PERIOD_MS);
|
||||
}
|
||||
}
|
||||
|
||||
void lora32_dump_regs(lora32_cfg_t *lora) {
|
||||
for(uint8_t i = 0; i < 127; i++) {
|
||||
printf("0x%2X: 0x%2X\n", i, lora32_read_reg(lora, i));
|
||||
}
|
||||
}
|
||||
|
||||
void lora32_toggle_reset(lora32_cfg_t *config) {
|
||||
// toggle reset (L/H)
|
||||
ESP_LOGI(TAG, "Toggling reset pin %d", config->reset);
|
||||
|
||||
gpio_set_level(config->reset, 0);
|
||||
vTaskDelay(100 / portTICK_PERIOD_MS); // requires 100us
|
||||
|
||||
gpio_set_level(config->reset, 1);
|
||||
vTaskDelay(100 / portTICK_PERIOD_MS); // 5ms before available
|
||||
}
|
||||
|
||||
void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor) {
|
||||
ESP_LOGI(TAG, "lora32_set_spreadfactor: %d", factor);
|
||||
|
||||
if(factor <= 6) {
|
||||
factor = 6;
|
||||
|
||||
lora32_write_reg(lora, REG_DETECTION_OPTIMIZE, DETECT_OPT_SF6);
|
||||
lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_SF6);
|
||||
} else {
|
||||
if(factor > 12) factor = 12;
|
||||
|
||||
lora32_write_reg(lora, REG_DETECTION_OPTIMIZE, DETECT_OPT_OTHER);
|
||||
lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER);
|
||||
}
|
||||
|
||||
lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0));
|
||||
}
|
||||
|
||||
void lora32_enable_continous_rx(lora32_cfg_t *lora) {
|
||||
ESP_LOGD(TAG, "enabling continuous receive");
|
||||
|
||||
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
|
||||
}
|
||||
|
||||
void lora32_handle_dio0(void *arg) {
|
||||
lora32_cfg_t *lora = (lora32_cfg_t*)arg;
|
||||
static uint8_t msg[MAX_PKT_LENGTH];
|
||||
|
||||
while(1) {
|
||||
if(xQueueReceive(dio0_evt_queue, lora, portMAX_DELAY)) {
|
||||
ESP_LOGI(TAG, "handling DIO0");
|
||||
|
||||
memset(msg, 0, MAX_PKT_LENGTH);
|
||||
|
||||
// read IRQ flags
|
||||
uint8_t irqs = lora32_read_reg(lora, REG_IRQ_FLAGS);
|
||||
// clear IRQ flags
|
||||
lora32_write_reg(lora, REG_IRQ_FLAGS, irqs);
|
||||
|
||||
// TODO: read packet length
|
||||
uint8_t len = lora32_read_reg(lora, lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES);
|
||||
ESP_LOGD(TAG, "lora32_handle_dio0 packet length: %d", len);
|
||||
|
||||
// TODO: set FIFO address to RX address
|
||||
uint8_t fifo_addr = lora32_read_reg(lora, REG_FIFO_RX_CURRENT_ADDR);
|
||||
ESP_LOGD(TAG, "lora32_handle_dio0 current FIFO address: %d", fifo_addr);
|
||||
|
||||
lora32_write_reg(lora, REG_FIFO_ADDR_PTR, fifo_addr);
|
||||
|
||||
uint8_t i = 0;
|
||||
for(; i < len; i++) {
|
||||
msg[lora->fifoIdx] = lora32_read_reg(lora, REG_FIFO);
|
||||
|
||||
lora->fifoIdx++;
|
||||
}
|
||||
|
||||
ESP_LOGD(TAG, "lora32_handle_dio0: %s", msg);
|
||||
|
||||
lora->fifoIdx = 0;
|
||||
lora32_write_reg(lora, REG_FIFO_ADDR_PTR, 0);
|
||||
|
||||
lora->receive((uint8_t*)&msg, len);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void IRAM_ATTR lora32_on_dio0(void *arg) {
|
||||
uint8_t i = 0;
|
||||
|
||||
xQueueSendFromISR(dio0_evt_queue, &i, NULL);
|
||||
}
|
||||
|
||||
uint8_t lora32_init(lora32_cfg_t *lora) {
|
||||
ESP_LOGD(TAG, "lora32_init");
|
||||
|
||||
// set pin outputs
|
||||
gpio_config_t io_conf;
|
||||
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
|
||||
io_conf.mode = GPIO_MODE_OUTPUT;
|
||||
io_conf.pin_bit_mask = (1ULL<<lora->reset)|(1ULL<<lora->nss);
|
||||
io_conf.pull_down_en = 0;
|
||||
io_conf.pull_up_en = 0;
|
||||
gpio_config(&io_conf);
|
||||
|
||||
lora32_toggle_reset(lora);
|
||||
|
||||
// set NSS high
|
||||
ESP_LOGI(TAG, "Bringing NSS high: %d", lora->nss);
|
||||
gpio_set_level(lora->nss, 1);
|
||||
|
||||
vTaskDelay(10 / portTICK_PERIOD_MS);
|
||||
|
||||
// init spi
|
||||
ESP_LOGI(TAG, "Initializing SPI bus");
|
||||
ESP_LOGI(TAG, "\n MISO: %d\nMOSI: %d\nCLK: %d\nNSS: %d", PIN_NUM_MISO, PIN_NUM_MOSI, PIN_NUM_CLK, lora->nss);
|
||||
|
||||
spi_bus_config_t buscfg = {
|
||||
.miso_io_num = PIN_NUM_MISO,
|
||||
.mosi_io_num = PIN_NUM_MOSI,
|
||||
.sclk_io_num = PIN_NUM_CLK,
|
||||
.quadwp_io_num = -1,
|
||||
.quadhd_io_num = -1
|
||||
};
|
||||
|
||||
spi_device_interface_config_t devcfg = {
|
||||
.clock_speed_hz = 8E6,
|
||||
.flags = 0,
|
||||
.mode = 0,
|
||||
.spics_io_num = lora->nss,
|
||||
.queue_size = 7,
|
||||
};
|
||||
|
||||
ESP_ERROR_CHECK(spi_bus_initialize(HSPI_HOST, &buscfg, 0));
|
||||
ESP_ERROR_CHECK(spi_bus_add_device(HSPI_HOST, &devcfg, &lora->spi));
|
||||
|
||||
uint8_t version = lora32_read_reg(lora, REG_VERSION);
|
||||
ESP_LOGD(TAG, "lora32_get_id() == 0x%2X", version);
|
||||
assert(version == 0x12);
|
||||
|
||||
// TODO: confirm this is happening. Before/after power measurements?
|
||||
lora32_sleep(lora);
|
||||
ESP_LOGI(TAG, "lora32_sleep");
|
||||
|
||||
// TODO: VERIFY
|
||||
lora32_set_frequency(lora, lora->frequency);
|
||||
ESP_LOGI(TAG, "lora32_set_frequency: %lu", lora->frequency);
|
||||
|
||||
lora32_write_reg(lora, REG_FIFO_TX_BASE_ADDR, 0x00);
|
||||
lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00);
|
||||
ESP_LOGI(TAG, "clear rx/tx fifos");
|
||||
|
||||
uint8_t lna = lora32_read_reg(lora, REG_LNA);
|
||||
lora32_write_reg(lora, REG_LNA, lna | 0x03);
|
||||
ESP_LOGI(TAG, "set lna: 0x%2X", lna | 0x03);
|
||||
|
||||
lora32_write_reg(lora, REG_MODEM_CONFIG_3, 0x04);
|
||||
//ESP_LOGI(TAG, "REG_MODEM_CONFIG_3: 0x%2X", lora32_read_reg(spi, REG_MODEM_CONFIG_3));
|
||||
|
||||
lora32_set_tx_power(lora, 17, PA_OUTPUT_PA_BOOST_PIN);
|
||||
ESP_LOGI(TAG, "lora32_set_tx_power");
|
||||
|
||||
lora32_idle(lora);
|
||||
ESP_LOGI(TAG, "lora32_idle");
|
||||
|
||||
//ESP_LOGI(TAG, "REG_OP_MODE: 0x%2X", lora32_read_reg(spi, REG_OP_MODE));
|
||||
|
||||
if(lora->receive != NULL) {
|
||||
ESP_LOGI(TAG, "Setting callback handler");
|
||||
|
||||
dio0_evt_queue = xQueueCreate(10, sizeof(uint8_t));
|
||||
|
||||
io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
|
||||
io_conf.pin_bit_mask = (1ULL << CONFIG_LORA32_DIO0_PIN);
|
||||
io_conf.mode = GPIO_MODE_INPUT;
|
||||
io_conf.pull_down_en = 0;
|
||||
io_conf.pull_up_en = 0;
|
||||
gpio_config(&io_conf);
|
||||
|
||||
gpio_set_intr_type(CONFIG_LORA32_DIO0_PIN, GPIO_INTR_POSEDGE);
|
||||
gpio_install_isr_service(0);
|
||||
|
||||
gpio_isr_handler_add(CONFIG_LORA32_DIO0_PIN, lora32_on_dio0, (void*)lora);
|
||||
|
||||
// this should probably be high priority
|
||||
xTaskCreate(&lora32_handle_dio0, "lora32_handle_dio0", 2048, lora, 6, NULL);
|
||||
|
||||
lora32_write_reg(lora, REG_DIO_MAPPING_1, 0x00);
|
||||
|
||||
lora32_enable_continous_rx(lora);
|
||||
}
|
||||
|
||||
if(lora->poll_rx) {
|
||||
ESP_LOGI(TAG, "enabling rx polling");
|
||||
|
||||
xTaskCreate(&lora32_poll_rx, "lora32_poll_rx", 2048, lora, 6, NULL);
|
||||
}
|
||||
|
||||
//lora32_dump_regs(spi);
|
||||
|
||||
return 1;
|
||||
};
|
||||
Loading…
Reference in New Issue