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reworking power level and lna code

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Morgan 'ARR\!' Allen 2020-04-16 20:57:50 -07:00
parent a062ed4dcb
commit 50d7497c0f
2 changed files with 37 additions and 10 deletions
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1
include/esp32-lora.h
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@ -36,6 +36,7 @@
#define REG_SYNC_WORD 0x39
#define REG_DIO_MAPPING_1 0x40
#define REG_VERSION 0x42
#define REG_PA_DAC 0x4D
// modes
#define MODE_SLEEP 0x00

46
main/esp32-lora.c
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@ -165,29 +165,44 @@ void lora32_set_frequency(lora32_cfg_t *lora, long frequency) {
ESP_LOGI(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
ESP_LOGI(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16) & 0xFF);
lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8) & 0xFF);
lora32_write_reg(lora, REG_FRF_LSB, (uint8_t)(frf >> 0) & 0xFF);
lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16));
lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8));
lora32_write_reg(lora, REG_FRF_LSB, (uint8_t)(frf >> 0));
ESP_LOGD(TAG, "REG_FRF_MSB: 0x%2X", lora32_read_reg(lora, REG_FRF_MSB));
ESP_LOGD(TAG, "REG_FRF_MID: 0x%2X", lora32_read_reg(lora, REG_FRF_MID));
ESP_LOGD(TAG, "REG_FRF_LSB: 0x%2X", lora32_read_reg(lora, REG_FRF_LSB));
}
void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
ESP_LOGI(TAG, "set_tx_power(%d, %d)", level, output);
void lora32_set_ocp(lora32_cfg_t *lora, uint8_t ma) {
}
void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
if(output == PA_OUTPUT_RFO_PIN) {
if(level > 14) level = 14;
lora32_write_reg(lora, REG_PA_CONFIG, 0x70 | level);
} else {
if(level < 2) level = 2;
else if(level > 17) level = 17;
if(level > 17) {
// cap power level to 20
if(level > 20) level = 20;
level -= 3;
lora32_write_reg(lora, REG_PA_DAC, 0x07);
// TODO: set over current protection
} else {
if(level < 2) level = 2;
lora32_write_reg(lora, REG_PA_DAC, 0x04);
// TODO: set over current protection
}
lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2));
}
ESP_LOGI(TAG, "set_tx_power(%d, %d)", level, output);
ESP_LOGD(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(lora, REG_PA_CONFIG));
}
@ -291,6 +306,18 @@ void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr) {
lora32_write_reg(lora, REG_MODEM_CONFIG_1, (lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xF1) | (cr << 1));
}
void lora32_set_lna(lora32_cfg_t *lora, uint8_t gain) {
// clamp gain values between 0b001 & 0b110
// NOTE: don't clamp until full REG_LNA is implmented
//if(gain == 0) gain = 1;
//else if(gain > 6) gain = 6;
uint8_t lna = lora32_read_reg(lora, REG_LNA);
lora32_write_reg(lora, REG_LNA, lna | gain);
ESP_LOGI(TAG, "set lna: 0x%2X", lna | gain);
}
static void lora32_handle_receive(lora32_cfg_t *lora) {
uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
ESP_LOGD(TAG, "lora32_handle_receive packet length: %d", len);
@ -429,10 +456,9 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00);
ESP_LOGI(TAG, "clear rx/tx fifos");
uint8_t lna = lora32_read_reg(lora, REG_LNA);
lora32_write_reg(lora, REG_LNA, lna | 0x03);
ESP_LOGI(TAG, "set lna: 0x%2X", lna | 0x03);
lora32_set_lna(lora, 0x03);
// enabling AGC
lora32_write_reg(lora, REG_MODEM_CONFIG_3, 0x04);
// TODO make based on config