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7141d87680
2 changed files with 63 additions and 183 deletions
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@ -23,13 +23,12 @@
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#define REG_IRQ_FLAGS 0x12
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#define REG_RX_NB_BYTES 0x13
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#define REG_PKT_RSSI_VALUE 0x1a
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#define REG_RSSI_VALUE 0x1b
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#define REG_PKT_SNR_VALUE 0x1b
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#define REG_MODEM_CONFIG_1 0x1d
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#define REG_MODEM_CONFIG_2 0x1e
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#define REG_PREAMBLE_MSB 0x20
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#define REG_PREAMBLE_LSB 0x21
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_HOP_PERIOD 0x24
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#define REG_MODEM_CONFIG_3 0x26
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#define REG_RSSI_WIDEBAND 0x2c
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#define REG_DETECTION_OPTIMIZE 0x31
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@ -78,27 +77,7 @@
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#define EV_DIO0 (1 << 0)
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#define ERR_LOR_VERSION_MISMATCH (01)
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#define LORA32_DEFAULT_CONFIG {\
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.bandwidth = B250,\
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.codingRate = 5,\
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.frequency = 915000000,\
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.spreadingFactor = 11,\
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.preamble = DEFAULT_PREAMBLE,\
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.implicitHeader = false,\
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.useCRC = false,\
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.fifoIdx = 0,\
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.copi = -1,\
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.cipo = -1,\
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.clk = -1,\
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.dio0 = -1,\
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.dio1 = -1,\
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.dio2 = -1,\
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.nss = -1,\
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.reset = -1,\
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.spi_host = 1,\
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}
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#define ERR_LOR_ID_MISMATCH (00)
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enum freq {
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F433, F866, F915
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@ -123,29 +102,23 @@ typedef struct {
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} lora32_handle_t;
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typedef struct lora32_cfg_t {
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uint8_t nss;
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uint8_t cipo;
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uint8_t copi;
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uint8_t clk;
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uint8_t dio0;
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uint8_t reset;
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uint8_t fifoIdx;
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uint8_t channel;
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uint8_t bandwidth;
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uint8_t spreadingFactor;
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uint8_t codingRate;
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int8_t nss;
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int8_t cipo;
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int8_t copi;
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int8_t clk;
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int8_t reset;
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int8_t dio0;
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int8_t dio1;
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int8_t dio2;
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int8_t channels[64];
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long frequency;
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uint8_t bandwidth;
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uint8_t spreadingFactor;
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uint8_t codingRate;
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uint16_t preamble;
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bool useCRC;
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bool implicitHeader;
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bool enableFHSS;
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receiveCallback receive;
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txdoneCallback tx_done;
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@ -161,24 +134,16 @@ typedef struct lora32_cfg_t {
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uint8_t lora32_spi_init(lora32_cfg_t *config);
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uint8_t lora32_init(lora32_cfg_t *config);
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uint8_t lora32_data_available(lora32_cfg_t *lora);
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int16_t lora32_get_packet_rssi(lora32_cfg_t *lora);
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int16_t lora32_get_rssi(lora32_cfg_t *lora);
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double lora32_calc_datarate(lora32_cfg_t *lora);
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void lora32_dump_regs(lora32_cfg_t *lora);
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void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period);
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void lora32_enable_continuous_rx(lora32_cfg_t *lora);
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void lora32_enable_single_rx(lora32_cfg_t *lora);
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void lora32_enable_cad(lora32_cfg_t *lora);
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void lora32_disable_fhss(lora32_cfg_t *lora);
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void lora32_toggle_reset(lora32_cfg_t *lora);
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void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
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void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw);
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void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr);
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void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
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uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora);
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void lora32_read_data(lora32_cfg_t *lora, uint8_t *data);
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void lora32_sleep(lora32_cfg_t *lora);
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void lora32_standby(lora32_cfg_t *lora);
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#endif // _LORA32_H__
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@ -31,7 +31,7 @@ static TaskHandle_t dio_task_handle;
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static SemaphoreHandle_t spi_semaphore;
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uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
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xSemaphoreTake(spi_semaphore, portMAX_DELAY);
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//xSemaphoreTake(spi_semaphore, portMAX_DELAY);
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spi_transaction_t t;
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memset(&t, 0, sizeof(spi_transaction_t));
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@ -45,13 +45,13 @@ uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
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ESP_LOGV(TAG, "<%2X<%2X", address, t.rx_data[1]);
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xSemaphoreGive(spi_semaphore);
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//xSemaphoreGive(spi_semaphore);
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return t.rx_data[1];
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}
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void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
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xSemaphoreTake(spi_semaphore, portMAX_DELAY);
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//xSemaphoreTake(spi_semaphore, portMAX_DELAY);
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spi_device_handle_t spi = lora->spi;
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@ -67,60 +67,44 @@ void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
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ESP_ERROR_CHECK(spi_device_transmit(spi, &t));
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xSemaphoreGive(spi_semaphore);
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//xSemaphoreGive(spi_semaphore);
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};
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double lora32_calc_datarate(lora32_cfg_t *lora) {
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double cr = (4.0 / (long)lora->codingRate);
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double sf = pow(2, lora->spreadingFactor);
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double c2 = sf / bandwidths[lora->bandwidth];
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ESP_LOGD(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2);
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ESP_LOGI(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2);
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return lora->spreadingFactor * cr / c2 * 1000;
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}
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void lora23_set_explicit_header(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "setting explicit header");
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lora->implicitHeader = false;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE);
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}
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void lora23_set_implicit_header(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "setting implicit header");
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lora->implicitHeader = true;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) | 0x01);
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}
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void lora32_standby(lora32_cfg_t *lora) {
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ESP_LOGV(TAG, "MODE_STANDBY");
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void lora32_idle(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "MODE_STANDBY");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STANDBY);
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}
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void lora32_sleep(lora32_cfg_t *lora) {
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ESP_LOGV(TAG, "MODE_SLEEP");
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ESP_LOGD(TAG, "MODE_SLEEP");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
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}
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void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period) {
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lora->enableFHSS = true;
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lora32_write_reg(lora, REG_HOP_PERIOD, period);
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}
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void lora32_disable_fhss(lora32_cfg_t *lora) {
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lora->enableFHSS = false;
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lora32_write_reg(lora, REG_HOP_PERIOD, 0);
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}
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void lora32_enable_tx(lora32_cfg_t *lora) {
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lora32_standby(lora);
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lora32_idle(lora);
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if(lora->implicitHeader)
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lora23_set_implicit_header(lora);
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@ -133,7 +117,7 @@ void lora32_enable_tx(lora32_cfg_t *lora) {
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}
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void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
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ESP_ERROR_CHECK(spi_device_acquire_bus(lora->spi, portMAX_DELAY));
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spi_device_acquire_bus(lora->spi, portMAX_DELAY);
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lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE);
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@ -151,12 +135,12 @@ void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
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}
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void lora32_set_frequency(lora32_cfg_t *lora, long frequency) {
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ESP_LOGD(TAG, "lora32_set_frequency: %lu", frequency);
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ESP_LOGI(TAG, "lora32_set_frequency: %lu", frequency);
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uint64_t frf = ((uint64_t)frequency << 19) / 32000000;
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ESP_LOGD(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
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ESP_LOGD(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
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ESP_LOGD(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
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ESP_LOGI(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
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ESP_LOGI(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
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ESP_LOGI(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
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lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16));
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lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8));
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@ -194,7 +178,7 @@ void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
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lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2));
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}
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ESP_LOGD(TAG, "set_tx_power(%d, %d)", level, output);
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ESP_LOGI(TAG, "set_tx_power(%d, %d)", level, output);
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ESP_LOGD(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(lora, REG_PA_CONFIG));
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}
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@ -231,7 +215,7 @@ void lora32_dump_regs(lora32_cfg_t *lora) {
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void lora32_toggle_reset(lora32_cfg_t *config) {
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// toggle reset (L/H)
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ESP_LOGD(TAG, "Toggling reset pin %d", config->reset);
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ESP_LOGI(TAG, "Toggling reset pin %d", config->reset);
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gpio_set_level(config->reset, 0);
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vTaskDelay(100 / portTICK_PERIOD_MS); // requires 100us
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@ -240,7 +224,7 @@ void lora32_toggle_reset(lora32_cfg_t *config) {
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vTaskDelay(100 / portTICK_PERIOD_MS); // 5ms before available
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}
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uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora) {
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uint8_t lora32_get_spreadingfactor(lora32_cfg_t *lora) {
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return (lora32_read_reg(lora, REG_MODEM_CONFIG_2) >> 4);
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}
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@ -257,23 +241,9 @@ void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor) {
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lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER);
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}
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ESP_LOGV(TAG, "lora32_set_spreadfactor: %d", factor);
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ESP_LOGI(TAG, "lora32_set_spreadfactor: %d", factor);
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lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0));
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lora->spreadingFactor = factor;
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}
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void lora32_enable_single_rx(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "MODE_RX_SINGLE");
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if(lora->receive != NULL) {
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lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
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}
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lora32_standby(lora);
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
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}
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void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
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@ -283,8 +253,6 @@ void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
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lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
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}
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lora32_standby(lora);
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
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}
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@ -300,44 +268,34 @@ void lora32_enable_cad(lora32_cfg_t *lora) {
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_CAD_DETECT);
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}
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int16_t lora32_get_rssi(lora32_cfg_t *lora) {
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// TODO support LF output constant of -164
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return -157 + lora32_read_reg(lora, REG_RSSI_VALUE);
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}
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int16_t lora32_get_packet_rssi(lora32_cfg_t *lora) {
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// TODO support LF output constant of -164
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return -157 + lora32_read_reg(lora, REG_PKT_RSSI_VALUE);
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}
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long lora32_get_bandwidth(lora32_cfg_t *lora) {
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uint8_t bw = (lora32_read_reg(lora, REG_MODEM_CONFIG_1) >> 4);
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ESP_LOGV(TAG, "lora32_get_bandwidth: %d", bw);
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ESP_LOGI(TAG, "lora32_get_bandwidth: %d", bw);
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if(bw > 9) return -1;
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ESP_LOGD(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]);
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ESP_LOGI(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]);
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return bandwidths[bw];
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}
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void lora32_set_ldo_flag(lora32_cfg_t *lora) {
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long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadfactor(lora)));
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long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadingfactor(lora)));
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ESP_LOGD(TAG, "symbolDuration: %ld", symbolDuration);
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ESP_LOGI(TAG, "symbolDuration: %ld", symbolDuration);
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bool ldoOn = symbolDuration > 16;
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ESP_LOGD(TAG, "ldoOn: %d", ldoOn);
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ESP_LOGI(TAG, "ldoOn: %d", ldoOn);
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uint8_t modem_config_3 = lora32_read_reg(lora, REG_MODEM_CONFIG_3);
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ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3);
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ESP_LOGI(TAG, "modem_config_3: %d", modem_config_3);
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modem_config_3 |= ldoOn << 3;
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ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3);
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ESP_LOGI(TAG, "modem_config_3: %d", modem_config_3);
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lora32_write_reg(lora, REG_MODEM_CONFIG_3, modem_config_3);
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}
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void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw) {
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ESP_LOGD(TAG, "lora32_set_bandwidth: %d", bw);
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ESP_LOGI(TAG, "lora32_set_bandwidth: %d", bw);
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uint8_t modem_config_1 = lora32_read_reg(lora, REG_MODEM_CONFIG_1);
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, (modem_config_1 & 0x0F) | (bw << 4));
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@ -351,7 +309,7 @@ void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr) {
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cr = cr - 4;
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ESP_LOGD(TAG, "lora32_set_coding_rate: %d", cr + 4);
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ESP_LOGI(TAG, "lora32_set_coding_rate: %d", cr + 4);
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, (lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xF1) | (cr << 1));
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}
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@ -365,7 +323,7 @@ void lora32_set_lna(lora32_cfg_t *lora, uint8_t gain) {
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uint8_t lna = lora32_read_reg(lora, REG_LNA);
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lora32_write_reg(lora, REG_LNA, lna | gain);
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ESP_LOGD(TAG, "set lna: 0x%2X", lna | gain);
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ESP_LOGI(TAG, "set lna: 0x%2X", lna | gain);
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}
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static void lora32_handle_receive(lora32_cfg_t *lora) {
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@ -384,11 +342,11 @@ static void lora32_handle_receive(lora32_cfg_t *lora) {
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static void IRAM_ATTR lora32_dio_task(void *arg) {
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// allocate lora32_cfg_t to receive config from Queu
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lora32_cfg_t *lora = malloc(sizeof(lora32_cfg_t));
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ESP_LOGD(TAG, "starting DIO handler task");
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ESP_LOGI(TAG, "starting DIO handler task");
|
||||
|
||||
while(1) {
|
||||
// wait for event over Queue
|
||||
if(xQueueReceive(dio_event_queue, (void*)&lora, portMAX_DELAY) != pdPASS) continue;
|
||||
if(xQueueReceive(dio_event_queue, (void*)lora, portMAX_DELAY) != pdPASS) continue;
|
||||
|
||||
// need a better way to log which event and from which config
|
||||
//ESP_LOGI(TAG, "handling DIO0 on GPIO%d", lora->dio0);
|
||||
|
|
@ -403,8 +361,6 @@ static void IRAM_ATTR lora32_dio_task(void *arg) {
|
|||
ESP_LOGD(TAG, "clearing irqs");
|
||||
lora32_write_reg(lora, REG_IRQ_FLAGS, irqs);
|
||||
|
||||
spi_device_release_bus(lora->spi);
|
||||
|
||||
// TODO handle header validation
|
||||
if((irqs & IRQ_RX_DONE) == IRQ_RX_DONE) {
|
||||
lora32_handle_receive(lora);
|
||||
|
|
@ -430,20 +386,7 @@ static void IRAM_ATTR lora32_dio_task(void *arg) {
|
|||
if(lora->cad_done != NULL) lora->cad_done(lora, cad_detected);
|
||||
}
|
||||
|
||||
if((irqs & IRQ_FHSS_CHANGE) == IRQ_FHSS_CHANGE) {
|
||||
ESP_LOGD(TAG, "switching channel %d: %d", lora->channel, lora->channels[lora->channel]);
|
||||
|
||||
if(lora->channel == 0 && lora->channels[lora->channel] == 0) continue;
|
||||
|
||||
if(lora->channels[lora->channel] == 0) {
|
||||
ESP_LOGD(TAG, "reseting to channel 0");
|
||||
lora->channel = 0;
|
||||
}
|
||||
|
||||
lora32_set_frequency(lora, lora->frequency + (lora->channels[lora->channel] * bandwidths[lora->bandwidth]));
|
||||
|
||||
lora->channel++;
|
||||
}
|
||||
spi_device_release_bus(lora->spi);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -451,19 +394,19 @@ void lora32_read_data(lora32_cfg_t *lora, uint8_t *data) {
|
|||
uint8_t i = 0;
|
||||
uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
|
||||
|
||||
ESP_LOGD(TAG, "Reading %d bytes", len);
|
||||
ESP_LOGI(TAG, "Reading %d bytes", len);
|
||||
|
||||
for(i = 0; i < len; i++) {
|
||||
data[i] = lora32_read_reg(lora, REG_FIFO);
|
||||
}
|
||||
}
|
||||
|
||||
static void IRAM_ATTR lora32_on_dio(void *arg) {
|
||||
xQueueSendFromISR(dio_event_queue, (void*)&arg, pdFALSE);
|
||||
static void IRAM_ATTR lora32_on_dio0(void *arg) {
|
||||
xQueueSend(dio_event_queue, arg, (TickType_t)0);
|
||||
}
|
||||
|
||||
uint8_t lora32_spi_init(lora32_cfg_t *lora) {
|
||||
ESP_LOGD(TAG, "Initializing SPI bus");
|
||||
ESP_LOGI(TAG, "Initializing SPI bus");
|
||||
|
||||
esp_err_t err = ESP_OK;
|
||||
|
||||
|
|
@ -499,7 +442,7 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
|
|||
|
||||
lora32_toggle_reset(lora);
|
||||
// set NSS high
|
||||
ESP_LOGD(TAG, "Bringing NSS high: %d", lora->nss);
|
||||
ESP_LOGI(TAG, "Bringing NSS high: %d", lora->nss);
|
||||
gpio_set_level(lora->nss, 1);
|
||||
|
||||
vTaskDelay(10 / portTICK_PERIOD_MS);
|
||||
|
|
@ -520,19 +463,11 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
|
|||
|
||||
uint8_t version = lora32_read_reg(lora, REG_VERSION);
|
||||
ESP_LOGD(TAG, "lora32_get_id() == 0x%2X", version);
|
||||
|
||||
lora->version = version;
|
||||
|
||||
// if ID does not match, something is likely wrong on the SPI bus
|
||||
if(version != 0x12) {
|
||||
ESP_LOGE(TAG, "REG_VERSION returned incorrectly. Expected 0x12 got 0x%02X", version);
|
||||
|
||||
return ERR_LOR_VERSION_MISMATCH;
|
||||
}
|
||||
assert(version == 0x12);
|
||||
|
||||
// TODO: confirm this is happening. Before/after power measurements?
|
||||
lora32_sleep(lora);
|
||||
ESP_LOGV(TAG, "lora32_sleep");
|
||||
ESP_LOGI(TAG, "lora32_sleep");
|
||||
|
||||
// TODO: VERIFY
|
||||
lora32_set_frequency(lora, lora->frequency);
|
||||
|
|
@ -542,7 +477,7 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
|
|||
|
||||
lora32_write_reg(lora, REG_FIFO_TX_BASE_ADDR, 0x00);
|
||||
lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00);
|
||||
ESP_LOGV(TAG, "clear rx/tx fifos");
|
||||
ESP_LOGI(TAG, "clear rx/tx fifos");
|
||||
|
||||
lora32_set_lna(lora, 0x03);
|
||||
|
||||
|
|
@ -551,61 +486,41 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
|
|||
|
||||
// TODO make based on config
|
||||
lora32_set_tx_power(lora, 17, PA_OUTPUT_PA_BOOST_PIN);
|
||||
ESP_LOGV(TAG, "lora32_set_tx_power");
|
||||
ESP_LOGI(TAG, "lora32_set_tx_power");
|
||||
|
||||
lora32_standby(lora);
|
||||
ESP_LOGV(TAG, "lora32_standby");
|
||||
|
||||
if(lora->implicitHeader)
|
||||
lora23_set_implicit_header(lora);
|
||||
else
|
||||
lora23_set_explicit_header(lora);
|
||||
lora32_idle(lora);
|
||||
ESP_LOGI(TAG, "lora32_idle");
|
||||
|
||||
// TODO setup shouldn't be based on just receive callback
|
||||
if(lora->receive != NULL) {
|
||||
ESP_LOGV(TAG, "Setting GPIO Interrupt");
|
||||
|
||||
// TODO check at least one DIOx pin is not NULL
|
||||
|
||||
uint64_t pin_bit_mask = 0;
|
||||
if(lora->dio0 > -1)
|
||||
pin_bit_mask |= (1 << lora->dio0);
|
||||
if(lora->dio1 > -1)
|
||||
pin_bit_mask |= (1 << lora->dio1);
|
||||
if(lora->dio2 > -1)
|
||||
pin_bit_mask |= (1 << lora->dio2);
|
||||
ESP_LOGI(TAG, "Setting GPIO Interrupt");
|
||||
|
||||
io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
|
||||
io_conf.pin_bit_mask = pin_bit_mask;
|
||||
io_conf.pin_bit_mask = (1ULL << lora->dio0);
|
||||
io_conf.mode = GPIO_MODE_INPUT;
|
||||
io_conf.pull_down_en = 1;
|
||||
io_conf.pull_down_en = 0;
|
||||
io_conf.pull_up_en = 0;
|
||||
gpio_config(&io_conf);
|
||||
|
||||
gpio_set_intr_type(lora->dio0, GPIO_INTR_POSEDGE);
|
||||
|
||||
// the DIO interrupt handling for every device is done from one task
|
||||
if(dio_task_handle == NULL) {
|
||||
ESP_LOGV(TAG, "Setting callback handler and ISR service");
|
||||
ESP_LOGI(TAG, "Setting callback handler and ISR service");
|
||||
|
||||
// enable global ISR service
|
||||
gpio_install_isr_service(0);
|
||||
|
||||
dio_event_queue = xQueueCreate(10, sizeof(lora32_cfg_t *));
|
||||
dio_event_queue = xQueueCreate(10, sizeof(lora32_cfg_t));
|
||||
|
||||
// this should probably be high priority
|
||||
xTaskCreate(&lora32_dio_task, "lora32_dio_task", 4096, NULL, 6, &dio_task_handle);
|
||||
}
|
||||
|
||||
// add ISR handler to the global service started (once) above
|
||||
ESP_LOGV(TAG, "Installing ISR handler for GPIO%d", lora->dio0);
|
||||
if(lora->dio0 > -1)
|
||||
gpio_isr_handler_add(lora->dio0, lora32_on_dio, (void*)lora);
|
||||
|
||||
if(lora->dio1 > -1)
|
||||
gpio_isr_handler_add(lora->dio1, lora32_on_dio, (void*)lora);
|
||||
|
||||
if(lora->dio2 > -1)
|
||||
gpio_isr_handler_add(lora->dio2, lora32_on_dio, (void*)lora);
|
||||
ESP_LOGI(TAG, "Installing ISR handler for GPIO%d", lora->dio0);
|
||||
gpio_isr_handler_add(lora->dio0, lora32_on_dio0, lora);
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
return 1;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue