211 lines
5.7 KiB
C
211 lines
5.7 KiB
C
#ifndef _LORA32_H__
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#define _LORA32_H__
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#include "driver/spi_common.h"
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#include "driver/spi_master.h"
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#include "freertos/event_groups.h"
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#define REG_FIFO 0x00
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#define REG_OP_MODE 0x01
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#define REG_BR_MSB 0x02
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#define REG_BR_LSB 0x03
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#define REG_FD_MSB 0x04
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#define REG_FD_LSB 0x05
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#define REG_FRF_MSB 0x06
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#define REG_FRF_MID 0x07
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#define REG_FRF_LSB 0x08
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#define REG_PA_CONFIG 0x09
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#define REG_LNA 0x0c
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#define REG_FIFO_ADDR_PTR 0x0d
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#define REG_FIFO_TX_BASE_ADDR 0x0e
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#define REG_FIFO_RX_BASE_ADDR 0x0f
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#define REG_FIFO_RX_CURRENT_ADDR 0x10
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#define REG_IRQ_FLAGS 0x12
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#define REG_RX_NB_BYTES 0x13
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#define REG_MODEM_STATUS 0x18
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#define REG_PKT_RSSI_VALUE 0x1a
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#define REG_RSSI_VALUE 0x1b
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#define REG_MODEM_CONFIG_1 0x1d
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#define REG_MODEM_CONFIG_2 0x1e
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#define REG_PREAMBLE_MSB 0x20
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#define REG_PREAMBLE_LSB 0x21
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_HOP_PERIOD 0x24
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#define REG_MODEM_CONFIG_3 0x26
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#define REG_RSSI_WIDEBAND 0x2c
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#define REG_DETECTION_OPTIMIZE 0x31
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#define REG_DETECTION_THRESHOLD 0x37
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#define REG_SYNC_WORD 0x39
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#define REG_DIO_MAPPING_1 0x40
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#define REG_DIO_MAPPING_2 0x41
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#define REG_VERSION 0x42
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#define REG_PA_DAC 0x4D
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// modes
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#define MODE_SLEEP 0x00
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#define MODE_STANDBY 0x01
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#define MODE_TX 0x03
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#define MODE_RX_CONTINUOUS 0x05
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#define MODE_RX_SINGLE 0x06
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#define MODE_CAD_DETECT 0x07
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#define MODE_LONG_RANGE_MODE 0x80
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// PA config
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#define PA_BOOST 0x80
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// IRQ masks
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#define IRQ_RX_TIMEOUT 0x80
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#define IRQ_RX_DONE 0x40
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#define IRQ_PAYLOAD_CRC_ERROR 0x20
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#define IRQ_VALID_HEADER 0x10
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#define IRQ_TX_DONE 0x08
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#define IRQ_CAD_DONE 0x04
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#define IRQ_FHSS_CHANGE 0x02
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#define IRQ_CAD_DETECTED 0x01
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#define MAX_PKT_LENGTH 255
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#define DETECT_OPT_SF6 0xC5
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#define DETECT_THRES_SF6 0x0C
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#define DETECT_OPT_OTHER 0xC3
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#define DETECT_THRES_OTHER 0x0A
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#define DEFAULT_SF 7
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#define DEFAULT_PREAMBLE 8
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#define DEFAULT_CR 5
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#define DIO0_MODE_SHIFT 6
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#define DIO0_MODE_RXDONE 0b00
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#define DIO0_MODE_TXDONE 0b01
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#define DIO0_MODE_CADDON 0b10
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#define DIO1_MODE_SHIFT 4
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#define DIO1_MODE_RXTIME 0b00
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#define DIO1_MODE_FHSSCC 0b01
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#define DIO1_MODE_CADDET 0b10
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#define DIO3_MODE_SHIFT 2
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#define DIO3_MODE_CADDON 0b00
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#define DIO3_MODE_HEADVA 0b01
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#define DIO3_MODE_CRCERR 0b10
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#define DIO4_MODE_CADDET 0b00
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#define DIO4_MODE_PLLLOC 0b10
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#define DIO4_MODE_SHIFT 6
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#define DIO5_MODE_SHIFT 4
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#define ERR_LOR_VERSION_MISMATCH (01)
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#define LORA32_DEFAULT_CONFIG() {\
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.bandwidth = 7,\
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.codingRate = 5,\
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.frequency = 915000000,\
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.spreadingFactor = 11,\
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.preamble = DEFAULT_PREAMBLE,\
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.implicitHeader = false,\
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.useCRC = false,\
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.fifoIdx = 0,\
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.copi = 23,\
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.cipo = 19,\
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.clk = 18,\
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.dio0 = -1,\
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.dio1 = -1,\
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.dio2 = -1,\
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.nss = -1,\
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.reset = -1,\
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.spi_host = 1,\
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}
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enum freq {
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F433, F866, F915
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} lora32_freq;
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typedef enum {
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B78, B104, B156, B208, B3125, B417, B625, B125, B250, B500
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} bandwidth;
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extern const long long frequencies[3];
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extern const long bandwidths[10];
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typedef struct lora32_cfg_t lora32_cfg_t;
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typedef void (*receiveCallback)(lora32_cfg_t *lora, uint8_t size);
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typedef void (*txdoneCallback)(lora32_cfg_t *lora);
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typedef void (*cadDoneCallback)(lora32_cfg_t *lora, bool detected);
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typedef void (*cadDetectedCallback)(lora32_cfg_t *lora);
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typedef struct {
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EventGroupHandle_t events;
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} lora32_handle_t;
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typedef struct lora32_modem_status_t {
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unsigned int detected:1;
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unsigned int synced:1;
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unsigned int rx:1;
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unsigned int valid:1;
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unsigned int clear:1;
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unsigned int cr:3;
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} lora32_modem_status_t;
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typedef struct lora32_cfg_t {
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uint8_t fifoIdx;
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uint8_t channel;
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uint8_t bandwidth;
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uint8_t spreadingFactor;
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uint8_t codingRate;
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uint8_t version; // to be written on init by the driver
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int8_t nss;
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int8_t cipo;
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int8_t copi;
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int8_t clk;
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int8_t reset;
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int8_t dio0;
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int8_t dio1;
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int8_t dio2;
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int8_t channels[64];
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long frequency;
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uint16_t preamble;
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bool useCRC;
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bool implicitHeader;
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bool enableFHSS;
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receiveCallback receive;
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txdoneCallback tx_done;
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cadDoneCallback cad_done;
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cadDetectedCallback cad_detected;
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uint8_t spi_host;
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spi_device_handle_t spi;
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lora32_handle_t handle;
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} lora32_cfg_t;
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uint8_t lora32_spi_init(lora32_cfg_t *config);
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uint8_t lora32_init(lora32_cfg_t *config);
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uint8_t lora32_data_available(lora32_cfg_t *lora);
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int16_t lora32_get_packet_rssi(lora32_cfg_t *lora);
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int16_t lora32_get_rssi(lora32_cfg_t *lora);
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double lora32_calc_datarate(lora32_cfg_t *lora);
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void lora32_dump_regs(lora32_cfg_t *lora);
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void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period);
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void lora32_enable_continuous_rx(lora32_cfg_t *lora);
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void lora32_enable_single_rx(lora32_cfg_t *lora);
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void lora32_enable_cad(lora32_cfg_t *lora);
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void lora32_disable_fhss(lora32_cfg_t *lora);
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void lora32_toggle_reset(lora32_cfg_t *lora);
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void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
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void lora32_set_bandwidth(lora32_cfg_t *lora, bandwidth bw);
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void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr);
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void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
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uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora);
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void lora32_read_data(lora32_cfg_t *lora, uint8_t *data);
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void lora32_sleep(lora32_cfg_t *lora);
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void lora32_standby(lora32_cfg_t *lora);
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#endif // _LORA32_H__
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