636 lines
18 KiB
C
636 lines
18 KiB
C
#include <string.h>
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#include <math.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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#include "esp_log.h"
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#include "esp_heap_caps.h"
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#include "driver/gpio.h"
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#include "driver/spi_common.h"
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#include "driver/spi_master.h"
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#include "driver/spi_common_internal.h"
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#include "esp32-lora.h"
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#define READ_REG 0x7F
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#define WRITE_REG 0x80
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#define PA_OUTPUT_RFO_PIN 0
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#define PA_OUTPUT_PA_BOOST_PIN 1
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const long long frequencies[] = { 433e+6, 866e+6, 915e+6 };
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const long bandwidths[] = { 7.8e3, 10.4e3, 15.6e3, 20.8e3, 31.25e3, 41.7e3, 62.5e3, 125e3, 250e3, 500e3 };
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const char *TAG = "LoRa32";
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static QueueHandle_t dio_event_queue;
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static TaskHandle_t dio_task_handle;
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static SemaphoreHandle_t spi_semaphore;
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uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
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xSemaphoreTake(spi_semaphore, portMAX_DELAY);
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spi_transaction_t t;
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memset(&t, 0, sizeof(spi_transaction_t));
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t.length = 16;
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t.flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA;
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t.tx_data[0] = address & READ_REG;
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t.tx_data[1] = 0x00;
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ESP_ERROR_CHECK(spi_device_transmit(lora->spi, &t));
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ESP_LOGV(TAG, "<%2X<%2X", address, t.rx_data[1]);
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xSemaphoreGive(spi_semaphore);
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return t.rx_data[1];
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}
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void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
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xSemaphoreTake(spi_semaphore, portMAX_DELAY);
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spi_device_handle_t spi = lora->spi;
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spi_transaction_t t;
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memset(&t, 0, sizeof(spi_transaction_t));
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ESP_LOGV(TAG, ">%2X>%2X", address, value);
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t.length = 16;
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t.flags = SPI_TRANS_USE_TXDATA;
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t.tx_data[0] = address | WRITE_REG;
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t.tx_data[1] = value;
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ESP_ERROR_CHECK(spi_device_transmit(spi, &t));
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xSemaphoreGive(spi_semaphore);
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};
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void lora32_update_dio_mapping(lora32_cfg_t *lora, uint8_t reg, uint8_t value, uint8_t shift) {
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uint8_t regdio1 = lora32_read_reg(lora, reg);
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// clear bits
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regdio1 &= ~(0b11 << shift);
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// set new values
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regdio1 |= (value << shift);
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lora32_write_reg(lora, reg, regdio1);
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}
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double lora32_calc_datarate(lora32_cfg_t *lora) {
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double cr = (4.0 / (long)lora->codingRate);
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double sf = pow(2, lora->spreadingFactor);
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double c2 = sf / bandwidths[lora->bandwidth];
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ESP_LOGD(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2);
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return lora->spreadingFactor * cr / c2 * 1000;
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}
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void lora32_set_explicit_header(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "setting explicit header");
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lora->implicitHeader = false;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE);
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}
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void lora32_set_implicit_header(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "setting implicit header");
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lora->implicitHeader = true;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) | 0x01);
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}
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void lora32_standby(lora32_cfg_t *lora) {
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ESP_LOGV(TAG, "MODE_STANDBY");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STANDBY);
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}
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void lora32_sleep(lora32_cfg_t *lora) {
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ESP_LOGV(TAG, "MODE_SLEEP");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
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}
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void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period) {
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lora->enableFHSS = true;
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lora32_write_reg(lora, REG_HOP_PERIOD, period);
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}
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void lora32_disable_fhss(lora32_cfg_t *lora) {
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lora->enableFHSS = false;
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lora32_write_reg(lora, REG_HOP_PERIOD, 0);
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}
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void lora32_enable_tx(lora32_cfg_t *lora) {
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lora32_standby(lora);
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if(lora->implicitHeader)
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lora32_set_implicit_header(lora);
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else
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lora32_set_explicit_header(lora);
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// zero out receive buffer
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lora32_write_reg(lora, REG_FIFO_ADDR_PTR, 0);
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lora32_write_reg(lora, REG_PAYLOAD_LENGTH, 0);
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}
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void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
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if(lora == NULL) return;
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ESP_ERROR_CHECK(spi_device_acquire_bus(lora->spi, portMAX_DELAY));
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lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE, DIO0_MODE_SHIFT);
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lora32_enable_tx(lora);
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uint8_t i = 0;
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for(; (i < len && i < MAX_PKT_LENGTH); i++)
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lora32_write_reg(lora, REG_FIFO, data[i]);
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lora32_write_reg(lora, REG_PAYLOAD_LENGTH, len);
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
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spi_device_release_bus(lora->spi);
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}
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void lora32_set_frequency(lora32_cfg_t *lora, long frequency) {
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ESP_LOGD(TAG, "lora32_set_frequency: %lu", frequency);
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uint64_t frf = ((uint64_t)frequency << 19) / 32000000;
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ESP_LOGD(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
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ESP_LOGD(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
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ESP_LOGD(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
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lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16));
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lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8));
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lora32_write_reg(lora, REG_FRF_LSB, (uint8_t)(frf >> 0));
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ESP_LOGD(TAG, "REG_FRF_MSB: 0x%2X", lora32_read_reg(lora, REG_FRF_MSB));
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ESP_LOGD(TAG, "REG_FRF_MID: 0x%2X", lora32_read_reg(lora, REG_FRF_MID));
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ESP_LOGD(TAG, "REG_FRF_LSB: 0x%2X", lora32_read_reg(lora, REG_FRF_LSB));
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}
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void lora32_set_ocp(lora32_cfg_t *lora, uint8_t ma) {
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}
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void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
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if(output == PA_OUTPUT_RFO_PIN) {
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if(level > 14) level = 14;
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lora32_write_reg(lora, REG_PA_CONFIG, 0x70 | level);
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} else {
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if(level > 17) {
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// cap power level to 20
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if(level > 20) level = 20;
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level -= 3;
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lora32_write_reg(lora, REG_PA_DAC, 0x07);
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// TODO: set over current protection
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} else {
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if(level < 2) level = 2;
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lora32_write_reg(lora, REG_PA_DAC, 0x04);
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// TODO: set over current protection
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}
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lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2));
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}
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ESP_LOGD(TAG, "set_tx_power(%d, %d)", level, output);
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ESP_LOGD(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(lora, REG_PA_CONFIG));
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}
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uint8_t lora32_data_available(lora32_cfg_t *lora) {
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return lora32_read_reg(lora, REG_RX_NB_BYTES) - lora->fifoIdx;
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}
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void lora32_dump_regs(lora32_cfg_t *lora) {
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uint8_t i;
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char endline[17] = {0};
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printf(" ");
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for(i = 0; i < 16; i++)
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printf(" %X%s", i, (i % 2 == 1 ? " " : ""));
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printf("\n");
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for(i = 0; i < 127; i++) {
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if(i % 16 == 0)
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printf("0x%02X: ", i);
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char c = lora32_read_reg(lora, i);
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endline[i % 16] = (c >= 32 ? c : '.');
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printf("%02X%s", c, i % 2 == 1 ? " " : "");
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if(i % 16 == 15)
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printf(" %s\n", endline);
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}
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printf("\n");
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}
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void lora32_toggle_reset(lora32_cfg_t *config) {
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// toggle reset (L/H)
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ESP_LOGD(TAG, "Toggling reset pin %d", config->reset);
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gpio_set_level(config->reset, 0);
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vTaskDelay(100 / portTICK_PERIOD_MS); // requires 100us
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gpio_set_level(config->reset, 1);
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vTaskDelay(100 / portTICK_PERIOD_MS); // 5ms before available
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}
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uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora) {
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return (lora32_read_reg(lora, REG_MODEM_CONFIG_2) >> 4);
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}
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void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor) {
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if(factor <= 6) {
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factor = 6;
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lora32_write_reg(lora, REG_DETECTION_OPTIMIZE, DETECT_OPT_SF6);
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lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_SF6);
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} else {
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if(factor > 12) factor = 12;
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lora32_write_reg(lora, REG_DETECTION_OPTIMIZE, DETECT_OPT_OTHER);
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lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER);
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}
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ESP_LOGV(TAG, "lora32_set_spreadfactor: %d", factor);
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lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0));
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lora->spreadingFactor = factor;
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}
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lora32_modem_status_t lora32_get_status(lora32_cfg_t *lora) {
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lora32_modem_status_t modem_status;
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uint8_t status = lora32_read_reg(lora, REG_MODEM_STATUS);
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memcpy(&modem_status, &status, 1);
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return modem_status;
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}
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void lora32_enable_single_rx(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "MODE_RX_SINGLE");
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lora32_standby(lora);
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if(lora->receive != NULL) {
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lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE, DIO0_MODE_SHIFT);
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}
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
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}
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void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "MODE_RX_CONTINUOUS");
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lora32_standby(lora);
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if(lora->receive != NULL) {
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lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE, DIO0_MODE_SHIFT);
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}
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
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}
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void lora32_enable_cad(lora32_cfg_t *lora) {
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lora32_standby(lora);
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if(lora->cad_done != NULL) {
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ESP_LOGV(TAG, "Setting DIO0 to CAD Done");
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lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO0_MODE_CADDON, DIO0_MODE_SHIFT);
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}
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if(lora->cad_detected != NULL) {
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ESP_LOGV(TAG, "Setting DIO1 to CAD Detect");
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lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO1_MODE_CADDET, DIO1_MODE_SHIFT);
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}
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ESP_LOGV(TAG, "MODE_CAD_DETECT");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_CAD_DETECT);
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}
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int16_t lora32_get_rssi(lora32_cfg_t *lora) {
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// TODO support LF output constant of -164
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return (-157 + lora32_read_reg(lora, REG_RSSI_VALUE)) & 0xffff;
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}
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int16_t lora32_get_packet_rssi(lora32_cfg_t *lora) {
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// TODO support LF output constant of -164
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return 0x0000 | (-157 + lora32_read_reg(lora, REG_PKT_RSSI_VALUE));
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}
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long lora32_get_bandwidth(lora32_cfg_t *lora) {
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uint8_t bw = (lora32_read_reg(lora, REG_MODEM_CONFIG_1) >> 4);
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ESP_LOGV(TAG, "lora32_get_bandwidth: %d", bw);
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if(bw > 9) return -1;
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ESP_LOGD(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]);
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return bandwidths[bw];
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}
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void lora32_set_ldo_flag(lora32_cfg_t *lora) {
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long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadfactor(lora)));
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ESP_LOGD(TAG, "symbolDuration: %ld", symbolDuration);
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bool ldoOn = symbolDuration > 16;
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ESP_LOGD(TAG, "ldoOn: %d", ldoOn);
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uint8_t modem_config_3 = lora32_read_reg(lora, REG_MODEM_CONFIG_3);
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ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3);
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modem_config_3 |= ldoOn << 3;
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ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3);
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lora32_write_reg(lora, REG_MODEM_CONFIG_3, modem_config_3);
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}
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void lora32_set_bandwidth(lora32_cfg_t *lora, bandwidth bw) {
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ESP_LOGD(TAG, "lora32_set_bandwidth: %d", bw);
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uint8_t modem_config_1 = lora32_read_reg(lora, REG_MODEM_CONFIG_1);
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, (modem_config_1 & 0x0F) | (bw << 4));
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lora32_set_ldo_flag(lora);
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}
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void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr) {
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if(cr < 5) cr = 5;
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else if(cr > 8) cr = 8;
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cr = cr - 4;
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ESP_LOGD(TAG, "lora32_set_coding_rate: %d", cr + 4);
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, (lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xF1) | (cr << 1));
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}
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void lora32_set_lna(lora32_cfg_t *lora, uint8_t gain) {
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// clamp gain values between 0b001 & 0b110
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// NOTE: don't clamp until full REG_LNA is implmented
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//if(gain == 0) gain = 1;
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//else if(gain > 6) gain = 6;
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uint8_t lna = lora32_read_reg(lora, REG_LNA);
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lora32_write_reg(lora, REG_LNA, lna | gain);
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ESP_LOGD(TAG, "set lna: 0x%2X", lna | gain);
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}
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static void lora32_handle_receive(lora32_cfg_t *lora) {
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uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
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ESP_LOGD(TAG, "lora32_handle_receive packet length: %d", len);
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// TODO: set FIFO address to RX address
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uint8_t fifo_addr = lora32_read_reg(lora, REG_FIFO_RX_CURRENT_ADDR);
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ESP_LOGD(TAG, "lora32_handle_receive current FIFO address: %d", fifo_addr);
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lora32_write_reg(lora, REG_FIFO_ADDR_PTR, fifo_addr);
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lora->receive(lora, len);
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}
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static void IRAM_ATTR lora32_dio_task(void *arg) {
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// allocate lora32_cfg_t to receive config from Queu
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lora32_cfg_t *lora = malloc(sizeof(lora32_cfg_t));
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ESP_LOGD(TAG, "starting DIO handler task");
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while(1) {
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// wait for event over Queue
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if(xQueueReceive(dio_event_queue, (void*)&lora, portMAX_DELAY) != pdPASS) continue;
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spi_device_acquire_bus(lora->spi, portMAX_DELAY);
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// read IRQ flags
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uint8_t irqs = lora32_read_reg(lora, REG_IRQ_FLAGS);
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ESP_LOGD(TAG, "reading irqs: 0x%02X", irqs);
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// clear IRQ flags by writing mask back
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ESP_LOGD(TAG, "clearing irqs");
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lora32_write_reg(lora, REG_IRQ_FLAGS, irqs);
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spi_device_release_bus(lora->spi);
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// TODO handle header validation
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if((irqs & IRQ_RX_DONE) == IRQ_RX_DONE) {
|
|
lora32_handle_receive(lora);
|
|
}
|
|
|
|
if((irqs & IRQ_TX_DONE) == IRQ_TX_DONE) {
|
|
if(lora->tx_done != NULL) lora->tx_done(lora);
|
|
}
|
|
|
|
bool cad_detected = false;
|
|
|
|
if((irqs & IRQ_CAD_DETECTED) == IRQ_CAD_DETECTED) {
|
|
// this is for the next clause, CAD Done callback gets true/false
|
|
cad_detected = true;
|
|
|
|
// no need for arg, cad_detected callback is always presummed true
|
|
if(lora->cad_detected != NULL) lora->cad_detected(lora);
|
|
}
|
|
|
|
if((irqs & IRQ_CAD_DONE) == IRQ_CAD_DONE) {
|
|
// cad_done gets true/false from above, when activity is detected
|
|
// these *should* fire at the same time, defaults to false
|
|
if(lora->cad_done != NULL) lora->cad_done(lora, cad_detected);
|
|
}
|
|
|
|
if((irqs & IRQ_FHSS_CHANGE) == IRQ_FHSS_CHANGE) {
|
|
ESP_LOGD(TAG, "switching channel %d: %d", lora->channel, lora->channels[lora->channel]);
|
|
|
|
if(lora->channel == 0 && lora->channels[lora->channel] == 0) continue;
|
|
|
|
if(lora->channels[lora->channel] == 0) {
|
|
ESP_LOGD(TAG, "reseting to channel 0");
|
|
lora->channel = 0;
|
|
}
|
|
|
|
lora32_set_frequency(lora, lora->frequency + (lora->channels[lora->channel] * bandwidths[lora->bandwidth]));
|
|
|
|
lora->channel++;
|
|
}
|
|
}
|
|
}
|
|
|
|
void lora32_read_data(lora32_cfg_t *lora, uint8_t *data) {
|
|
uint8_t i = 0;
|
|
uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
|
|
|
|
ESP_LOGD(TAG, "Reading %d bytes", len);
|
|
|
|
for(i = 0; i < len; i++) {
|
|
data[i] = lora32_read_reg(lora, REG_FIFO);
|
|
}
|
|
}
|
|
|
|
static void IRAM_ATTR lora32_on_dio(void *arg) {
|
|
xQueueSendFromISR(dio_event_queue, (void*)&arg, pdFALSE);
|
|
}
|
|
|
|
uint8_t lora32_spi_init(lora32_cfg_t *lora) {
|
|
ESP_LOGD(TAG, "Initializing SPI bus");
|
|
|
|
esp_err_t err = ESP_OK;
|
|
|
|
spi_bus_config_t buscfg = {
|
|
.miso_io_num = lora->cipo,
|
|
.mosi_io_num = lora->copi,
|
|
.sclk_io_num = lora->clk,
|
|
.quadwp_io_num = -1,
|
|
.quadhd_io_num = -1
|
|
};
|
|
|
|
if(spi_bus_get_attr(lora->spi_host) == NULL) {
|
|
// 2 should be SPI_DMA_CH_AUTO ??? but it doesn't seem to be defined
|
|
err = spi_bus_initialize(lora->spi_host, &buscfg, 2);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
uint8_t lora32_init(lora32_cfg_t *lora) {
|
|
esp_log_level_set(TAG, ESP_LOG_DEBUG);
|
|
|
|
if(spi_semaphore == NULL) {
|
|
spi_semaphore = xSemaphoreCreateMutex();
|
|
}
|
|
|
|
gpio_config_t io_conf;
|
|
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
|
|
io_conf.mode = GPIO_MODE_OUTPUT;
|
|
|
|
io_conf.pin_bit_mask = (1ULL<<lora->reset)|(1ULL<<lora->nss);
|
|
io_conf.pull_down_en = 0;
|
|
io_conf.pull_up_en = 0;
|
|
gpio_config(&io_conf);
|
|
|
|
lora32_toggle_reset(lora);
|
|
// set NSS high
|
|
ESP_LOGD(TAG, "Bringing NSS high: %d", lora->nss);
|
|
gpio_set_level(lora->nss, 1);
|
|
|
|
vTaskDelay(10 / portTICK_PERIOD_MS);
|
|
|
|
// SPI device setup
|
|
spi_device_interface_config_t devcfg = {
|
|
.clock_speed_hz = 8E6,
|
|
.flags = 0,
|
|
.mode = 0,
|
|
.spics_io_num = lora->nss,
|
|
.queue_size = 7,
|
|
};
|
|
|
|
ESP_ERROR_CHECK(spi_bus_add_device(lora->spi_host, &devcfg, &lora->spi));
|
|
|
|
// initialize event groups
|
|
lora->handle.events = xEventGroupCreate();
|
|
|
|
uint8_t version = lora32_read_reg(lora, REG_VERSION);
|
|
ESP_LOGD(TAG, "lora32_get_id() == 0x%2X", version);
|
|
|
|
lora->version = version;
|
|
|
|
// if ID does not match, something is likely wrong on the SPI bus
|
|
if(version != 0x12) {
|
|
ESP_LOGE(TAG, "REG_VERSION returned incorrectly. Expected 0x12 got 0x%02X", version);
|
|
|
|
return ERR_LOR_VERSION_MISMATCH;
|
|
}
|
|
|
|
// TODO: confirm this is happening. Before/after power measurements?
|
|
lora32_sleep(lora);
|
|
ESP_LOGV(TAG, "lora32_sleep");
|
|
|
|
// TODO: VERIFY
|
|
lora32_set_frequency(lora, lora->frequency);
|
|
lora32_set_spreadfactor(lora, lora->spreadingFactor);
|
|
lora32_set_bandwidth(lora, lora->bandwidth);
|
|
lora32_set_coding_rate(lora, lora->codingRate);
|
|
|
|
lora32_write_reg(lora, REG_FIFO_TX_BASE_ADDR, 0x00);
|
|
lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00);
|
|
ESP_LOGV(TAG, "clear rx/tx fifos");
|
|
|
|
lora32_set_lna(lora, 0x03);
|
|
|
|
// enable auto AGC
|
|
lora32_write_reg(lora, REG_MODEM_CONFIG_3, 0x04);
|
|
|
|
// TODO make based on config
|
|
lora32_set_tx_power(lora, 17, PA_OUTPUT_PA_BOOST_PIN);
|
|
ESP_LOGV(TAG, "lora32_set_tx_power");
|
|
|
|
lora32_standby(lora);
|
|
ESP_LOGV(TAG, "lora32_standby");
|
|
|
|
if(lora->implicitHeader)
|
|
lora32_set_implicit_header(lora);
|
|
else
|
|
lora32_set_explicit_header(lora);
|
|
|
|
// TODO setup shouldn't be based on just receive callback
|
|
if(lora->receive != NULL) {
|
|
ESP_LOGV(TAG, "Setting GPIO Interrupt");
|
|
|
|
// TODO check at least one DIOx pin is not NULL
|
|
|
|
uint64_t pin_bit_mask = 0;
|
|
if(lora->dio0 > -1)
|
|
pin_bit_mask |= (1 << lora->dio0);
|
|
if(lora->dio1 > -1)
|
|
pin_bit_mask |= (1 << lora->dio1);
|
|
if(lora->dio2 > -1)
|
|
pin_bit_mask |= (1 << lora->dio2);
|
|
|
|
io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
|
|
io_conf.pin_bit_mask = pin_bit_mask;
|
|
io_conf.mode = GPIO_MODE_INPUT;
|
|
io_conf.pull_down_en = 1;
|
|
io_conf.pull_up_en = 0;
|
|
gpio_config(&io_conf);
|
|
|
|
// the DIO interrupt handling for every device is done from one task
|
|
if(dio_task_handle == NULL) {
|
|
ESP_LOGV(TAG, "Setting callback handler and ISR service");
|
|
|
|
// enable global ISR service
|
|
gpio_install_isr_service(0);
|
|
|
|
dio_event_queue = xQueueCreate(10, sizeof(lora32_cfg_t *));
|
|
|
|
// this should probably be high priority
|
|
xTaskCreate(&lora32_dio_task, "lora32_dio_task", 4096, NULL, 6, &dio_task_handle);
|
|
}
|
|
|
|
// add ISR handler to the global service started (once) above
|
|
ESP_LOGV(TAG, "Installing ISR handler for GPIO%d", lora->dio0);
|
|
if(lora->dio0 > -1)
|
|
gpio_isr_handler_add(lora->dio0, lora32_on_dio, (void*)lora);
|
|
|
|
if(lora->dio1 > -1)
|
|
gpio_isr_handler_add(lora->dio1, lora32_on_dio, (void*)lora);
|
|
|
|
if(lora->dio2 > -1)
|
|
gpio_isr_handler_add(lora->dio2, lora32_on_dio, (void*)lora);
|
|
}
|
|
|
|
return ESP_OK;
|
|
};
|