455 lines
13 KiB
C
455 lines
13 KiB
C
#include <string.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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#include "esp_log.h"
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#include "esp_heap_caps.h"
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#include "driver/gpio.h"
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#include "driver/spi_common.h"
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#include "driver/spi_master.h"
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#include "esp32-lora.h"
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#define READ_REG 0x7F
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#define WRITE_REG 0x80
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#define PIN_NUM_MISO 19
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#define PIN_NUM_MOSI 27
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#define PIN_NUM_CLK 5
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#define PA_OUTPUT_RFO_PIN 0
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#define PA_OUTPUT_PA_BOOST_PIN 1
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const long long frequencies[] = { 433e+6, 866e+6, 915e+6 };
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const long bandwidths[] = { 7.8e+3, 10.4e+3, 15.6e+3, 20.8e+3, 31.25e+3, 41.7e+3, 62.5e+3, 125e+3, 250e+3 };
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const char *TAG = "LoRa32";
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lora32_cfg_t lora32_create() {
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static spi_device_handle_t spi;
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return (lora32_cfg_t){
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.bandwidth = bandwidths[B125],
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.codingRate = DEFAULT_CR,
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.dio0 = CONFIG_LORA32_DIO0_PIN,
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.implicitHeader = false,
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.nss = CONFIG_LORA32_NSS_PIN,
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.reset = CONFIG_LORA32_RESET_PIN,
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.frequency = 915000000,
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.preamble = DEFAULT_PREAMBLE,
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.spreadingFactor = DEFAULT_SF,
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.spi = spi,
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.receive = NULL,
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.useCRC = false,
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.fifoIdx = 0
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};
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}
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void lora32_send_cmd(lora32_cfg_t lora, uint8_t cmd, uint8_t value, uint8_t len, uint8_t *rx_buffer) {
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uint8_t tx_buffer[2];
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tx_buffer[0] = cmd;
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tx_buffer[1] = value;
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spi_transaction_t t;
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memset(&t, 0, sizeof(t));
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t.length = 8 * len;
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t.rxlength = 8 * len;
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t.tx_buffer = &tx_buffer;
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t.rx_buffer = rx_buffer;
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ESP_ERROR_CHECK(spi_device_transmit(lora.spi, &t));
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//ESP_LOGI(TAG, "send_cmd rx_data: 0x%2X 0x%2X", rx_buffer[0], rx_buffer[1]);
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}
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uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
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spi_transaction_t t;
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memset(&t, 0, sizeof(spi_transaction_t));
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t.length = 16;
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t.flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA;
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t.tx_data[0] = address & READ_REG;
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t.tx_data[1] = 0x00;
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ESP_ERROR_CHECK(spi_device_transmit(lora->spi, &t));
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ESP_LOGV(TAG, "<%2X<%2X", address, t.rx_data[1]);
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return t.rx_data[1];
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}
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void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
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spi_device_handle_t spi = lora->spi;
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spi_transaction_t t;
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memset(&t, 0, sizeof(spi_transaction_t));
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ESP_LOGV(TAG, ">%2X>%2X", address, value);
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t.length = 16;
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t.flags = SPI_TRANS_USE_TXDATA;
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t.tx_data[0] = address | WRITE_REG;
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t.tx_data[1] = value;
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ESP_ERROR_CHECK(spi_device_transmit(spi, &t));
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};
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void lora23_set_explicit_header(lora32_cfg_t *lora) {
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lora->implicitHeader = false;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE);
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}
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void lora23_set_implicit_header(lora32_cfg_t *lora) {
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lora->implicitHeader = true;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) | 0x01);
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}
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void lora32_idle(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "MODE_STANDBY");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STANDBY);
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}
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void lora32_sleep(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "MODE_SLEEP");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
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}
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void lora32_enable_tx(lora32_cfg_t *lora) {
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lora32_idle(lora);
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if(lora->implicitHeader)
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lora23_set_implicit_header(lora);
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else
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lora23_set_explicit_header(lora);
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// zero out receive buffer
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lora32_write_reg(lora, REG_FIFO_ADDR_PTR, 0);
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lora32_write_reg(lora, REG_PAYLOAD_LENGTH, 0);
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}
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void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
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lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE);
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lora32_enable_tx(lora);
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uint8_t i = 0;
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for(; (i < len && i < MAX_PKT_LENGTH); i++)
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lora32_write_reg(lora, REG_FIFO, data[i]);
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lora32_write_reg(lora, REG_PAYLOAD_LENGTH, len);
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
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}
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void lora32_set_frequency(lora32_cfg_t *lora, long frequency) {
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uint64_t frf = ((uint64_t)frequency << 19) / 32000000;
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ESP_LOGI(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
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ESP_LOGI(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
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ESP_LOGI(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
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lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16) & 0xFF);
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lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8) & 0xFF);
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lora32_write_reg(lora, REG_FRF_LSB, (uint8_t)(frf >> 0) & 0xFF);
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ESP_LOGD(TAG, "REG_FRF_MSB: 0x%2X", lora32_read_reg(lora, REG_FRF_MSB));
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ESP_LOGD(TAG, "REG_FRF_MID: 0x%2X", lora32_read_reg(lora, REG_FRF_MID));
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ESP_LOGD(TAG, "REG_FRF_LSB: 0x%2X", lora32_read_reg(lora, REG_FRF_LSB));
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}
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void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
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ESP_LOGI(TAG, "set_tx_power(%d, %d)", level, output);
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if(output == PA_OUTPUT_RFO_PIN) {
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if(level > 14) level = 14;
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lora32_write_reg(lora, REG_PA_CONFIG, 0x70 | level);
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} else {
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if(level < 2) level = 2;
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else if(level > 17) level = 17;
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lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2));
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}
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ESP_LOGD(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(lora, REG_PA_CONFIG));
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}
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uint8_t lora32_data_available(lora32_cfg_t *lora) {
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return lora32_read_reg(lora, REG_RX_NB_BYTES) - lora->fifoIdx;
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}
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void lora32_dump_regs(lora32_cfg_t *lora) {
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uint8_t i;
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char endline[17] = {0};
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printf(" ");
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for(i = 0; i < 16; i++)
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printf(" %X%s", i, (i % 2 == 1 ? " " : ""));
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printf("\n");
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for(i = 0; i < 127; i++) {
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if(i % 16 == 0)
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printf("0x%02X: ", i);
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char c = lora32_read_reg(lora, i);
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endline[i % 16] = (c >= 32 ? c : '.');
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printf("%02X%s", c, i % 2 == 1 ? " " : "");
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if(i % 16 == 15)
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printf(" %s\n", endline);
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}
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printf("\n");
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}
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void lora32_toggle_reset(lora32_cfg_t *config) {
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// toggle reset (L/H)
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ESP_LOGI(TAG, "Toggling reset pin %d", config->reset);
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gpio_set_level(config->reset, 0);
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vTaskDelay(100 / portTICK_PERIOD_MS); // requires 100us
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gpio_set_level(config->reset, 1);
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vTaskDelay(100 / portTICK_PERIOD_MS); // 5ms before available
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}
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void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor) {
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if(factor <= 6) {
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factor = 6;
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lora32_write_reg(lora, REG_DETECTION_OPTIMIZE, DETECT_OPT_SF6);
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lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_SF6);
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} else {
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if(factor > 12) factor = 12;
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lora32_write_reg(lora, REG_DETECTION_OPTIMIZE, DETECT_OPT_OTHER);
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lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER);
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}
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ESP_LOGI(TAG, "lora32_set_spreadfactor: %d", factor);
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lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0));
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}
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void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "MODE_RX_CONTINUOUS");
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if(lora->receive != NULL) {
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lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
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}
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
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}
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void lora32_enable_cad(lora32_cfg_t *lora) {
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if((lora->cad_done != NULL) | (lora->cad_detected != NULL)) {
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ESP_LOGD(TAG, "Setting DIO0 to CAD Detect");
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lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_CADDET);
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}
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ESP_LOGD(TAG, "MODE_CAD_DETECT");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_CAD_DETECT);
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}
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void lora32_set_bandwidth(lora32_cfg_t *lora, enum bandwidth bw) {
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uint8_t modem_config_1 = lora32_read_reg(lora, REG_MODEM_CONFIG_1);
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ESP_LOGI(TAG, "lora32_set_bandwidth: %d", bw);
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, (modem_config_1 & 0x0F) | (bw << 4));
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}
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void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr) {
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if(cr < 5) cr = 5;
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else if(cr > 8) cr = 8;
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cr = cr - 4;
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ESP_LOGI(TAG, "lora32_set_coding_rate: %d", cr + 4);
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, (lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xF1) | (cr << 1));
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}
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static void lora32_handle_receive(lora32_cfg_t *lora) {
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uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
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ESP_LOGD(TAG, "lora32_handle_receive packet length: %d", len);
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// TODO: set FIFO address to RX address
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uint8_t fifo_addr = lora32_read_reg(lora, REG_FIFO_RX_CURRENT_ADDR);
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ESP_LOGD(TAG, "lora32_handle_receive current FIFO address: %d", fifo_addr);
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lora32_write_reg(lora, REG_FIFO_ADDR_PTR, fifo_addr);
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lora->receive(len);
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}
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static void IRAM_ATTR lora32_dio0_task(void *arg) {
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lora32_cfg_t *lora = (lora32_cfg_t*)arg;
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ESP_LOGD(TAG, "starting DIO0 handler task");
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while(1) {
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EventBits_t evbits = xEventGroupWaitBits(lora->handle.events, EV_DIO0, pdTRUE, pdFALSE, 5000 / portTICK_PERIOD_MS);
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// timed out, loop and continue to wait
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if(evbits == 0) continue;
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ESP_LOGD(TAG, "handling DIO0");
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// read IRQ flags
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uint8_t irqs = lora32_read_reg(lora, REG_IRQ_FLAGS);
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ESP_LOGD(TAG, "reading irqs: %02X", irqs);
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// clear IRQ flags
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ESP_LOGD(TAG, "clearing irqs");
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lora32_write_reg(lora, REG_IRQ_FLAGS, irqs);
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// TODO handle header validation
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if((irqs & IRQ_RX_DONE) == IRQ_RX_DONE) {
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lora32_handle_receive(lora);
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}
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if((irqs & IRQ_TX_DONE) == IRQ_TX_DONE) {
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if(lora->tx_done != NULL) lora->tx_done();
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}
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bool cad_detected = false;
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if((irqs & IRQ_CAD_DETECTED) == IRQ_CAD_DETECTED) {
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// this is for the next clause, CAD Done callback gets true/false
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cad_detected = true;
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// no need for arg, cad_detected callback is always presummed true
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if(lora->cad_detected != NULL) lora->cad_detected();
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}
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if((irqs & IRQ_CAD_DONE) == IRQ_CAD_DONE) {
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// cad_done gets true/false from above, when activity is detected
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// these *should* fire at the same time, defaults to false
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if(lora->cad_done != NULL) lora->cad_done(cad_detected);
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}
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}
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}
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void lora32_read_data(lora32_cfg_t *lora, uint8_t *data) {
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uint8_t i = 0;
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uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
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ESP_LOGI(TAG, "Reading %d bytes", len);
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for(i = 0; i < len; i++) {
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data[i] = lora32_read_reg(lora, REG_FIFO);
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}
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}
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static void IRAM_ATTR lora32_on_dio0(void *arg) {
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BaseType_t woken = pdFALSE;
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xEventGroupSetBitsFromISR(((lora32_cfg_t*)arg)->handle.events, EV_DIO0, &woken);
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}
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uint8_t lora32_init(lora32_cfg_t *lora) {
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gpio_config_t io_conf;
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io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
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io_conf.mode = GPIO_MODE_OUTPUT;
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io_conf.pin_bit_mask = (1ULL<<lora->reset)|(1ULL<<lora->nss);
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io_conf.pull_down_en = 0;
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io_conf.pull_up_en = 0;
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gpio_config(&io_conf);
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lora32_toggle_reset(lora);
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// set NSS high
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ESP_LOGI(TAG, "Bringing NSS high: %d", lora->nss);
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gpio_set_level(lora->nss, 1);
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vTaskDelay(10 / portTICK_PERIOD_MS);
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// init spi
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ESP_LOGI(TAG, "Initializing SPI bus");
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// TODO fix this awkward log along with pin assignments in general
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ESP_LOGI(TAG, "\n MISO: %d\nMOSI: %d\nCLK: %d\nNSS: %d", PIN_NUM_MISO, PIN_NUM_MOSI, PIN_NUM_CLK, lora->nss);
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spi_bus_config_t buscfg = {
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.miso_io_num = PIN_NUM_MISO,
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.mosi_io_num = PIN_NUM_MOSI,
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.sclk_io_num = PIN_NUM_CLK,
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.quadwp_io_num = -1,
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.quadhd_io_num = -1
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};
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spi_device_interface_config_t devcfg = {
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.clock_speed_hz = 8E6,
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.flags = 0,
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.mode = 0,
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.spics_io_num = lora->nss,
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.queue_size = 7,
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};
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ESP_ERROR_CHECK(spi_bus_initialize(HSPI_HOST, &buscfg, 0));
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ESP_ERROR_CHECK(spi_bus_add_device(HSPI_HOST, &devcfg, &lora->spi));
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// initialize event groups
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lora->handle.events = xEventGroupCreate();
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uint8_t version = lora32_read_reg(lora, REG_VERSION);
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ESP_LOGD(TAG, "lora32_get_id() == 0x%2X", version);
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assert(version == 0x12);
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// TODO: confirm this is happening. Before/after power measurements?
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lora32_sleep(lora);
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ESP_LOGI(TAG, "lora32_sleep");
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// TODO: VERIFY
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lora32_set_frequency(lora, lora->frequency);
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ESP_LOGI(TAG, "lora32_set_frequency: %lu", lora->frequency);
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lora32_write_reg(lora, REG_FIFO_TX_BASE_ADDR, 0x00);
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lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00);
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ESP_LOGI(TAG, "clear rx/tx fifos");
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uint8_t lna = lora32_read_reg(lora, REG_LNA);
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lora32_write_reg(lora, REG_LNA, lna | 0x03);
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ESP_LOGI(TAG, "set lna: 0x%2X", lna | 0x03);
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lora32_write_reg(lora, REG_MODEM_CONFIG_3, 0x04);
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// TODO make based on config
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lora32_set_tx_power(lora, 17, PA_OUTPUT_PA_BOOST_PIN);
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ESP_LOGI(TAG, "lora32_set_tx_power");
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lora32_idle(lora);
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ESP_LOGI(TAG, "lora32_idle");
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// TODO setup shouldn't be based on just receive callback
|
|
if(lora->receive != NULL) {
|
|
ESP_LOGI(TAG, "Setting callback handler");
|
|
|
|
io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
|
|
io_conf.pin_bit_mask = (1ULL << CONFIG_LORA32_DIO0_PIN);
|
|
io_conf.mode = GPIO_MODE_INPUT;
|
|
io_conf.pull_down_en = 0;
|
|
io_conf.pull_up_en = 0;
|
|
gpio_config(&io_conf);
|
|
|
|
gpio_set_intr_type(CONFIG_LORA32_DIO0_PIN, GPIO_INTR_POSEDGE);
|
|
gpio_install_isr_service(0);
|
|
|
|
gpio_isr_handler_add(CONFIG_LORA32_DIO0_PIN, lora32_on_dio0, (void*)lora);
|
|
|
|
// this should probably be high priority
|
|
xTaskCreate(&lora32_dio0_task, "lora32_dio0_task", 14048, (void*)lora, 6, NULL);
|
|
}
|
|
|
|
return 1;
|
|
};
|