2018-07-28 14:33:15 -04:00
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#ifndef _LORA32_H__
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#define _LORA32_H__
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#include "driver/spi_common.h"
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#include "driver/spi_master.h"
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#define REG_FIFO 0x00
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#define REG_OP_MODE 0x01
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#define REG_BR_MSB 0x02
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#define REG_BR_LSB 0x03
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#define REG_FD_MSB 0x04
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#define REG_FD_LSB 0x05
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#define REG_FRF_MSB 0x06
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#define REG_FRF_MID 0x07
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#define REG_FRF_LSB 0x08
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#define REG_PA_CONFIG 0x09
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#define REG_LNA 0x0c
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#define REG_FIFO_ADDR_PTR 0x0d
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#define REG_FIFO_TX_BASE_ADDR 0x0e
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#define REG_FIFO_RX_BASE_ADDR 0x0f
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#define REG_FIFO_RX_CURRENT_ADDR 0x10
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#define REG_IRQ_FLAGS 0x12
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#define REG_RX_NB_BYTES 0x13
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#define REG_PKT_RSSI_VALUE 0x1a
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#define REG_PKT_SNR_VALUE 0x1b
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#define REG_MODEM_CONFIG_1 0x1d
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#define REG_MODEM_CONFIG_2 0x1e
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#define REG_PREAMBLE_MSB 0x20
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#define REG_PREAMBLE_LSB 0x21
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_MODEM_CONFIG_3 0x26
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#define REG_RSSI_WIDEBAND 0x2c
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#define REG_DETECTION_OPTIMIZE 0x31
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#define REG_DETECTION_THRESHOLD 0x37
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#define REG_SYNC_WORD 0x39
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#define REG_DIO_MAPPING_1 0x40
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#define REG_VERSION 0x42
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// modes
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#define MODE_LONG_RANGE_MODE 0x80
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#define MODE_SLEEP 0x00
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#define MODE_STANDBY 0x01
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#define MODE_TX 0x03
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#define MODE_RX_CONTINUOUS 0x05
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#define MODE_RX_SINGLE 0x06
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// PA config
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#define PA_BOOST 0x80
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// IRQ masks
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#define IRQ_TX_DONE_MASK 0x08
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#define IRQ_PAYLOAD_CRC_ERROR_MASK 0x20
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#define IRQ_RX_DONE_MASK 0x40
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#define MAX_PKT_LENGTH 255
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#define DETECT_OPT_SF6 0xC5
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#define DETECT_OPT_OTHER 0xC3
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#define DETECT_THRES_SF6 0x0C
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#define DETECT_THRES_OTHER 0x0A
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#define DEFAULT_SF 7
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#define DEFAULT_PREAMBLE 8
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#define DEFAULT_CR 5
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enum freq {
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F433, F866, F915
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} lora32_freq;
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const long long frequencies[3];
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const long bandwidths[9];
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enum bandwidth {
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B78, B104, B156, B208, B3125, B417, B625, B125, B250
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};
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typedef void (*receiveCallback)(uint8_t *data, uint8_t size);
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typedef struct lora32_cfg_t {
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uint8_t nss;
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uint8_t dio0;
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uint8_t reset;
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uint8_t fifoIdx;
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long frequency;
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enum bandwidth bandwidth;
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uint8_t spreadingFactor;
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uint8_t codingRate;
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uint16_t preamble;
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bool useCRC;
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bool implicitHeader;
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bool poll_rx;
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receiveCallback receive;
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spi_device_handle_t spi;
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} lora32_cfg_t;
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lora32_cfg_t lora32_create();
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uint8_t lora32_init(lora32_cfg_t *config);
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uint8_t lora32_data_available(lora32_cfg_t *lora);
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uint8_t lora32_parse_packet(lora32_cfg_t *lora, uint8_t size);
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void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
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void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
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void lora32_dump_regs(lora32_cfg_t *lora);
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2018-07-29 03:46:07 -04:00
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void lora32_enable_continous_rx(lora32_cfg_t *lora);
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2018-07-29 17:00:59 -04:00
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void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t d);
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2018-07-28 14:33:15 -04:00
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#endif // _LORA32_H__
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