cleanup of IRQ pin setting

lowered some log levels

include/esp32-lora.h

@@ -23,12 +23,13 @@
 #define REG_IRQ_FLAGS            0x12
 #define REG_RX_NB_BYTES          0x13
 #define REG_PKT_RSSI_VALUE       0x1a
-#define REG_PKT_SNR_VALUE        0x1b
+#define REG_RSSI_VALUE           0x1b
 #define REG_MODEM_CONFIG_1       0x1d
 #define REG_MODEM_CONFIG_2       0x1e
 #define REG_PREAMBLE_MSB         0x20
 #define REG_PREAMBLE_LSB         0x21
 #define REG_PAYLOAD_LENGTH       0x22
+#define REG_HOP_PERIOD           0x24
 #define REG_MODEM_CONFIG_3       0x26
 #define REG_RSSI_WIDEBAND        0x2c
 #define REG_DETECTION_OPTIMIZE   0x31
@@ -77,7 +78,27 @@
 
 #define EV_DIO0 (1 << 0)
 
-#define ERR_LOR_ID_MISMATCH (00)
+#define ERR_LOR_VERSION_MISMATCH (01)
+
+#define LORA32_DEFAULT_CONFIG {\
+  .bandwidth = B250,\
+  .codingRate = 5,\
+  .frequency = 915000000,\
+  .spreadingFactor = 11,\
+  .preamble = DEFAULT_PREAMBLE,\
+  .implicitHeader = false,\
+  .useCRC = false,\
+  .fifoIdx = 0,\
+  .copi = -1,\
+  .cipo = -1,\
+  .clk = -1,\
+  .dio0 = -1,\
+  .dio1 = -1,\
+  .dio2 = -1,\
+  .nss = -1,\
+  .reset = -1,\
+  .spi_host = 1,\
+}
 
 enum freq {
   F433, F866, F915
@@ -102,23 +123,29 @@ typedef struct {
 } lora32_handle_t;
 
 typedef struct lora32_cfg_t {
-  uint8_t nss;
-  uint8_t cipo;
-  uint8_t copi;
-  uint8_t clk;
-  uint8_t dio0;
-  uint8_t reset;
   uint8_t fifoIdx;
-
+  uint8_t channel;
-  long frequency;
   uint8_t bandwidth;
-
   uint8_t spreadingFactor;
   uint8_t codingRate;
+
+  int8_t nss;
+  int8_t cipo;
+  int8_t copi;
+  int8_t clk;
+  int8_t reset;
+  int8_t dio0;
+  int8_t dio1;
+  int8_t dio2;
+  int8_t channels[64];
+
+  long frequency;
+
   uint16_t preamble;
 
   bool useCRC;
   bool implicitHeader;
+  bool enableFHSS;
 
   receiveCallback receive;
   txdoneCallback tx_done;
@@ -134,16 +161,24 @@ typedef struct lora32_cfg_t {
 uint8_t lora32_spi_init(lora32_cfg_t *config);
 uint8_t lora32_init(lora32_cfg_t *config);
 uint8_t lora32_data_available(lora32_cfg_t *lora);
+int16_t lora32_get_packet_rssi(lora32_cfg_t *lora);
+int16_t lora32_get_rssi(lora32_cfg_t *lora);
 
 double lora32_calc_datarate(lora32_cfg_t *lora);
 void lora32_dump_regs(lora32_cfg_t *lora);
+void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period);
 void lora32_enable_continuous_rx(lora32_cfg_t *lora);
+void lora32_enable_single_rx(lora32_cfg_t *lora);
 void lora32_enable_cad(lora32_cfg_t *lora);
+void lora32_disable_fhss(lora32_cfg_t *lora);
 void lora32_toggle_reset(lora32_cfg_t *lora);
 void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
 void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw);
 void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr);
 void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
+uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora);
 void lora32_read_data(lora32_cfg_t *lora, uint8_t *data);
+void lora32_sleep(lora32_cfg_t *lora);
+void lora32_standby(lora32_cfg_t *lora);
 
 #endif // _LORA32_H__

main/esp32-lora.c

@@ -31,7 +31,7 @@ static TaskHandle_t dio_task_handle;
 static SemaphoreHandle_t spi_semaphore;
 
 uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
-  //xSemaphoreTake(spi_semaphore, portMAX_DELAY);
+  xSemaphoreTake(spi_semaphore, portMAX_DELAY);
 
 	spi_transaction_t t;
   memset(&t, 0, sizeof(spi_transaction_t));
@@ -45,13 +45,13 @@ uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
 
   ESP_LOGV(TAG, "<%2X<%2X", address, t.rx_data[1]);
 
-  //xSemaphoreGive(spi_semaphore);
+  xSemaphoreGive(spi_semaphore);
 
 	return t.rx_data[1];
 }
 
 void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
-  //xSemaphoreTake(spi_semaphore, portMAX_DELAY);
+  xSemaphoreTake(spi_semaphore, portMAX_DELAY);
 
   spi_device_handle_t spi = lora->spi;
 
@@ -67,44 +67,60 @@ void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
 
   ESP_ERROR_CHECK(spi_device_transmit(spi, &t));
 
-  //xSemaphoreGive(spi_semaphore);
+  xSemaphoreGive(spi_semaphore);
 };
 
 double lora32_calc_datarate(lora32_cfg_t *lora) {
   double cr = (4.0 / (long)lora->codingRate);
   double sf = pow(2, lora->spreadingFactor);
   double c2 = sf / bandwidths[lora->bandwidth];
-  ESP_LOGI(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2);
+  ESP_LOGD(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2);
 
   return lora->spreadingFactor * cr / c2 * 1000;
 }
 
 void lora23_set_explicit_header(lora32_cfg_t *lora) {
+  ESP_LOGD(TAG, "setting explicit header");
+
   lora->implicitHeader = false;
 
   lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE);
 }
 
 void lora23_set_implicit_header(lora32_cfg_t *lora) {
+  ESP_LOGD(TAG, "setting implicit header");
+
   lora->implicitHeader = true;
 
   lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) | 0x01);
 }
 
-void lora32_idle(lora32_cfg_t *lora) {
+void lora32_standby(lora32_cfg_t *lora) {
-  ESP_LOGD(TAG, "MODE_STANDBY");
+  ESP_LOGV(TAG, "MODE_STANDBY");
 
   lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STANDBY);
 }
 
 void lora32_sleep(lora32_cfg_t *lora) {
-  ESP_LOGD(TAG, "MODE_SLEEP");
+  ESP_LOGV(TAG, "MODE_SLEEP");
 
   lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
 }
 
+void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period) {
+  lora->enableFHSS = true;
+
+  lora32_write_reg(lora, REG_HOP_PERIOD, period);
+}
+
+void lora32_disable_fhss(lora32_cfg_t *lora) {
+  lora->enableFHSS = false;
+
+  lora32_write_reg(lora, REG_HOP_PERIOD, 0);
+}
+
 void lora32_enable_tx(lora32_cfg_t *lora) {
-  lora32_idle(lora);
+  lora32_standby(lora);
 
   if(lora->implicitHeader)
     lora23_set_implicit_header(lora);
@@ -117,7 +133,7 @@ void lora32_enable_tx(lora32_cfg_t *lora) {
 }
 
 void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
-  spi_device_acquire_bus(lora->spi, portMAX_DELAY);
+  ESP_ERROR_CHECK(spi_device_acquire_bus(lora->spi, portMAX_DELAY));
 
   lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE);
 
@@ -135,12 +151,12 @@ void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
 }
 
 void lora32_set_frequency(lora32_cfg_t *lora, long frequency) {
-  ESP_LOGI(TAG, "lora32_set_frequency: %lu", frequency);
+  ESP_LOGD(TAG, "lora32_set_frequency: %lu", frequency);
   uint64_t frf = ((uint64_t)frequency << 19) / 32000000;
 
-  ESP_LOGI(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
+  ESP_LOGD(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
-  ESP_LOGI(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >>  8));
+  ESP_LOGD(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >>  8));
-  ESP_LOGI(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >>  0));
+  ESP_LOGD(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >>  0));
 
   lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16));
   lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >>  8));
@@ -178,7 +194,7 @@ void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
     lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2));
   }
 
-  ESP_LOGI(TAG, "set_tx_power(%d, %d)", level, output);
+  ESP_LOGD(TAG, "set_tx_power(%d, %d)", level, output);
 
   ESP_LOGD(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(lora, REG_PA_CONFIG));
 }
@@ -215,7 +231,7 @@ void lora32_dump_regs(lora32_cfg_t *lora) {
 
 void lora32_toggle_reset(lora32_cfg_t *config) {
   // toggle reset (L/H)
-  ESP_LOGI(TAG, "Toggling reset pin %d", config->reset);
+  ESP_LOGD(TAG, "Toggling reset pin %d", config->reset);
 
   gpio_set_level(config->reset, 0);
   vTaskDelay(100 / portTICK_PERIOD_MS); // requires 100us
@@ -224,7 +240,7 @@ void lora32_toggle_reset(lora32_cfg_t *config) {
   vTaskDelay(100 / portTICK_PERIOD_MS); // 5ms before available
 }
 
-uint8_t lora32_get_spreadingfactor(lora32_cfg_t *lora) {
+uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora) {
   return (lora32_read_reg(lora, REG_MODEM_CONFIG_2) >> 4);
 }
 
@@ -241,9 +257,23 @@ void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor) {
     lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER);
   }
 
-  ESP_LOGI(TAG, "lora32_set_spreadfactor: %d", factor);
+  ESP_LOGV(TAG, "lora32_set_spreadfactor: %d", factor);
 
   lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0));
+
+  lora->spreadingFactor = factor;
+}
+
+void lora32_enable_single_rx(lora32_cfg_t *lora) {
+  ESP_LOGD(TAG, "MODE_RX_SINGLE");
+
+  if(lora->receive != NULL) {
+    lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
+  }
+
+  lora32_standby(lora);
+
+  lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
 }
 
 void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
@@ -253,6 +283,8 @@ void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
     lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
   }
 
+  lora32_standby(lora);
+
   lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
 }
 
@@ -268,34 +300,44 @@ void lora32_enable_cad(lora32_cfg_t *lora) {
   lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_CAD_DETECT);
 }
 
+int16_t lora32_get_rssi(lora32_cfg_t *lora) {
+  // TODO support LF output constant of -164
+  return -157 + lora32_read_reg(lora, REG_RSSI_VALUE);
+}
+
+int16_t lora32_get_packet_rssi(lora32_cfg_t *lora) {
+  // TODO support LF output constant of -164
+  return -157 + lora32_read_reg(lora, REG_PKT_RSSI_VALUE);
+}
+
 long lora32_get_bandwidth(lora32_cfg_t *lora) {
   uint8_t bw = (lora32_read_reg(lora, REG_MODEM_CONFIG_1) >> 4);
-  ESP_LOGI(TAG, "lora32_get_bandwidth: %d", bw);
+  ESP_LOGV(TAG, "lora32_get_bandwidth: %d", bw);
 
   if(bw > 9) return -1;
 
-  ESP_LOGI(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]);
+  ESP_LOGD(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]);
 
   return bandwidths[bw];
 }
 
 void lora32_set_ldo_flag(lora32_cfg_t *lora) {
-  long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadingfactor(lora)));
+  long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadfactor(lora)));
 
-  ESP_LOGI(TAG, "symbolDuration: %ld", symbolDuration);
+  ESP_LOGD(TAG, "symbolDuration: %ld", symbolDuration);
 
   bool ldoOn = symbolDuration > 16;
-  ESP_LOGI(TAG, "ldoOn: %d", ldoOn);
+  ESP_LOGD(TAG, "ldoOn: %d", ldoOn);
 
   uint8_t modem_config_3 = lora32_read_reg(lora, REG_MODEM_CONFIG_3);
-  ESP_LOGI(TAG, "modem_config_3: %d", modem_config_3);
+  ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3);
   modem_config_3 |= ldoOn << 3;
-  ESP_LOGI(TAG, "modem_config_3: %d", modem_config_3);
+  ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3);
   lora32_write_reg(lora, REG_MODEM_CONFIG_3, modem_config_3);
 }
 
 void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw) {
-  ESP_LOGI(TAG, "lora32_set_bandwidth: %d", bw);
+  ESP_LOGD(TAG, "lora32_set_bandwidth: %d", bw);
 
   uint8_t modem_config_1 = lora32_read_reg(lora, REG_MODEM_CONFIG_1);
   lora32_write_reg(lora, REG_MODEM_CONFIG_1, (modem_config_1 & 0x0F) | (bw << 4));
@@ -309,7 +351,7 @@ void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr) {
 
   cr = cr  - 4;
 
-  ESP_LOGI(TAG, "lora32_set_coding_rate: %d", cr + 4);
+  ESP_LOGD(TAG, "lora32_set_coding_rate: %d", cr + 4);
 
   lora32_write_reg(lora, REG_MODEM_CONFIG_1, (lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xF1) | (cr << 1));
 }
@@ -323,7 +365,7 @@ void lora32_set_lna(lora32_cfg_t *lora, uint8_t gain) {
   uint8_t lna = lora32_read_reg(lora, REG_LNA);
 
   lora32_write_reg(lora, REG_LNA, lna | gain);
-  ESP_LOGI(TAG, "set lna: 0x%2X", lna | gain);
+  ESP_LOGD(TAG, "set lna: 0x%2X", lna | gain);
 }
 
 static void lora32_handle_receive(lora32_cfg_t *lora) {
@@ -342,11 +384,11 @@ static void lora32_handle_receive(lora32_cfg_t *lora) {
 static void IRAM_ATTR lora32_dio_task(void *arg) {
   // allocate lora32_cfg_t to receive config from Queu
   lora32_cfg_t *lora = malloc(sizeof(lora32_cfg_t));
-  ESP_LOGI(TAG, "starting DIO handler task");
+  ESP_LOGD(TAG, "starting DIO handler task");
 
   while(1) {
     // wait for event over Queue
-    if(xQueueReceive(dio_event_queue, (void*)lora, portMAX_DELAY) != pdPASS) continue;
+    if(xQueueReceive(dio_event_queue, (void*)&lora, portMAX_DELAY) != pdPASS) continue;
 
     // need a better way to log which event and from which config
     //ESP_LOGI(TAG, "handling DIO0 on GPIO%d", lora->dio0);
@@ -361,6 +403,8 @@ static void IRAM_ATTR lora32_dio_task(void *arg) {
     ESP_LOGD(TAG, "clearing irqs");
     lora32_write_reg(lora, REG_IRQ_FLAGS, irqs);
 
+    spi_device_release_bus(lora->spi);
+
     // TODO handle header validation
     if((irqs & IRQ_RX_DONE) == IRQ_RX_DONE) {
       lora32_handle_receive(lora);
@@ -386,7 +430,20 @@ static void IRAM_ATTR lora32_dio_task(void *arg) {
       if(lora->cad_done != NULL) lora->cad_done(lora, cad_detected);
     }
 
-    spi_device_release_bus(lora->spi);
+    if((irqs & IRQ_FHSS_CHANGE) == IRQ_FHSS_CHANGE) {
+      ESP_LOGD(TAG, "switching channel %d: %d", lora->channel, lora->channels[lora->channel]);
+
+      if(lora->channel == 0 && lora->channels[lora->channel] == 0) continue;
+
+      if(lora->channels[lora->channel] == 0) {
+        ESP_LOGD(TAG, "reseting to channel 0");
+        lora->channel = 0;
+      }
+
+      lora32_set_frequency(lora, lora->frequency + (lora->channels[lora->channel] * bandwidths[lora->bandwidth]));
+
+      lora->channel++;
+    }
   }
 }
 
@@ -394,19 +451,19 @@ void lora32_read_data(lora32_cfg_t *lora, uint8_t *data) {
   uint8_t i = 0;
   uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
 
-  ESP_LOGI(TAG, "Reading %d bytes", len);
+  ESP_LOGD(TAG, "Reading %d bytes", len);
 
   for(i = 0; i < len; i++) {
     data[i] = lora32_read_reg(lora, REG_FIFO);
   }
 }
 
-static void IRAM_ATTR lora32_on_dio0(void *arg) {
+static void IRAM_ATTR lora32_on_dio(void *arg) {
-  xQueueSend(dio_event_queue, arg, (TickType_t)0);
+  xQueueSendFromISR(dio_event_queue, (void*)&arg, pdFALSE);
 }
 
 uint8_t lora32_spi_init(lora32_cfg_t *lora) {
-  ESP_LOGI(TAG, "Initializing SPI bus");
+  ESP_LOGD(TAG, "Initializing SPI bus");
 
   esp_err_t err = ESP_OK;
 
@@ -442,7 +499,7 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
 
   lora32_toggle_reset(lora);
   // set NSS high
-  ESP_LOGI(TAG, "Bringing NSS high: %d", lora->nss);
+  ESP_LOGD(TAG, "Bringing NSS high: %d", lora->nss);
   gpio_set_level(lora->nss, 1);
 
   vTaskDelay(10 / portTICK_PERIOD_MS);
@@ -463,11 +520,19 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
 
   uint8_t version = lora32_read_reg(lora, REG_VERSION);
   ESP_LOGD(TAG, "lora32_get_id() == 0x%2X", version);
-  assert(version == 0x12);
+
+  lora->version = version;
+
+  // if ID does not match, something is likely wrong on the SPI bus
+  if(version != 0x12) {
+    ESP_LOGE(TAG, "REG_VERSION returned incorrectly. Expected 0x12 got 0x%02X", version);
+
+    return ERR_LOR_VERSION_MISMATCH;
+  }
 
   // TODO: confirm this is happening. Before/after power measurements?
   lora32_sleep(lora);
-  ESP_LOGI(TAG, "lora32_sleep");
+  ESP_LOGV(TAG, "lora32_sleep");
 
   // TODO: VERIFY
   lora32_set_frequency(lora, lora->frequency);
@@ -477,7 +542,7 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
 
   lora32_write_reg(lora, REG_FIFO_TX_BASE_ADDR, 0x00);
   lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00);
-  ESP_LOGI(TAG, "clear rx/tx fifos");
+  ESP_LOGV(TAG, "clear rx/tx fifos");
   
   lora32_set_lna(lora, 0x03);
 
@@ -486,41 +551,61 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
 
   // TODO make based on config
   lora32_set_tx_power(lora, 17, PA_OUTPUT_PA_BOOST_PIN);
-  ESP_LOGI(TAG, "lora32_set_tx_power");
+  ESP_LOGV(TAG, "lora32_set_tx_power");
 
-  lora32_idle(lora);
+  lora32_standby(lora);
-  ESP_LOGI(TAG, "lora32_idle");
+  ESP_LOGV(TAG, "lora32_standby");
+
+  if(lora->implicitHeader)
+    lora23_set_implicit_header(lora);
+  else
+    lora23_set_explicit_header(lora);
 
   // TODO setup shouldn't be based on just receive callback
   if(lora->receive != NULL) {
-    ESP_LOGI(TAG, "Setting GPIO Interrupt");
+    ESP_LOGV(TAG, "Setting GPIO Interrupt");
+
+    // TODO check at least one DIOx pin is not NULL
+
+    uint64_t pin_bit_mask = 0;
+    if(lora->dio0 > -1)
+      pin_bit_mask |= (1 << lora->dio0);
+    if(lora->dio1 > -1)
+      pin_bit_mask |= (1 << lora->dio1);
+    if(lora->dio2 > -1)
+      pin_bit_mask |= (1 << lora->dio2);
 
     io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
-    io_conf.pin_bit_mask = (1ULL << lora->dio0);
+    io_conf.pin_bit_mask = pin_bit_mask;
     io_conf.mode = GPIO_MODE_INPUT;
-    io_conf.pull_down_en = 0;
+    io_conf.pull_down_en = 1;
     io_conf.pull_up_en = 0;
     gpio_config(&io_conf);
 
-    gpio_set_intr_type(lora->dio0, GPIO_INTR_POSEDGE);
-
     // the DIO interrupt handling for every device is done from one task
     if(dio_task_handle == NULL) {
-      ESP_LOGI(TAG, "Setting callback handler and ISR service");
+      ESP_LOGV(TAG, "Setting callback handler and ISR service");
 
       // enable global ISR service
       gpio_install_isr_service(0);
 
-      dio_event_queue = xQueueCreate(10, sizeof(lora32_cfg_t));
+      dio_event_queue = xQueueCreate(10, sizeof(lora32_cfg_t *));
 
       // this should probably be high priority
       xTaskCreate(&lora32_dio_task, "lora32_dio_task", 4096, NULL, 6, &dio_task_handle);
     }
 
     // add ISR handler to the global service started (once) above
-    ESP_LOGI(TAG, "Installing ISR handler for GPIO%d", lora->dio0);
+    ESP_LOGV(TAG, "Installing ISR handler for GPIO%d", lora->dio0);
-    gpio_isr_handler_add(lora->dio0, lora32_on_dio0, lora);
+    if(lora->dio0 > -1)
+      gpio_isr_handler_add(lora->dio0, lora32_on_dio, (void*)lora);
+
+    if(lora->dio1 > -1)
+      gpio_isr_handler_add(lora->dio1, lora32_on_dio, (void*)lora);
+
+    if(lora->dio2 > -1)
+      gpio_isr_handler_add(lora->dio2, lora32_on_dio, (void*)lora);
   }
 
-  return 1;
+  return ESP_OK;
 };