update GPIO const names

include/esp32-lora.h

@@ -22,6 +22,7 @@
 #define REG_FIFO_RX_CURRENT_ADDR 0x10
 #define REG_IRQ_FLAGS            0x12
 #define REG_RX_NB_BYTES          0x13
+#define REG_MODEM_STATUS         0x18
 #define REG_PKT_RSSI_VALUE       0x1a
 #define REG_RSSI_VALUE           0x1b
 #define REG_MODEM_CONFIG_1       0x1d
@@ -36,6 +37,7 @@
 #define REG_DETECTION_THRESHOLD  0x37
 #define REG_SYNC_WORD            0x39
 #define REG_DIO_MAPPING_1        0x40
+#define REG_DIO_MAPPING_2        0x41
 #define REG_VERSION              0x42
 #define REG_PA_DAC               0x4D
 
@@ -72,44 +74,55 @@
 #define DEFAULT_PREAMBLE 8
 #define DEFAULT_CR 5
 
-#define DIO0_MODE_RXDONE  0x00
+#define DIO0_MODE_SHIFT   6
-#define DIO0_MODE_TXDONE  0x40
+#define DIO0_MODE_RXDONE  0b00
-#define DIO0_MODE_CADDET  0x80
+#define DIO0_MODE_TXDONE  0b01
+#define DIO0_MODE_CADDON  0b10
 
-#define EV_DIO0 (1 << 0)
+#define DIO1_MODE_SHIFT   4
+#define DIO1_MODE_RXTIME  0b00
+#define DIO1_MODE_FHSSCC  0b01
+#define DIO1_MODE_CADDET  0b10
+
+#define DIO3_MODE_SHIFT   2
+#define DIO3_MODE_CADDON  0b00
+#define DIO3_MODE_HEADVA  0b01
+#define DIO3_MODE_CRCERR  0b10
+
+#define DIO4_MODE_CADDET  0b00
+#define DIO4_MODE_PLLLOC  0b10
+#define DIO4_MODE_SHIFT   6
+
+#define DIO5_MODE_SHIFT   4
 
 #define ERR_LOR_VERSION_MISMATCH (01)
 
-#define LORA32_DEFAULT_CONFIG {\
+#define LORA32_DEFAULT_CONFIG() {\
-  .bandwidth = B250,\
+  .bandwidth = 7,\
   .codingRate = 5,\
   .frequency = 915000000,\
-  .spreadingFactor = 11,\
+  .spreadingFactor = 8,\
   .preamble = DEFAULT_PREAMBLE,\
   .implicitHeader = false,\
   .useCRC = false,\
   .fifoIdx = 0,\
-  .copi = -1,\
+  .copi = 23,\
-  .cipo = -1,\
+  .cipo = 19,\
-  .clk = -1,\
+  .clk = 18,\
-  .dio0 = -1,\
+  .dio0 = 5,\
-  .dio1 = -1,\
+  .dio1 = 12,\
-  .dio2 = -1,\
+  .dio2 = 13,\
-  .nss = -1,\
+  .nss = 15,\
-  .reset = -1,\
+  .reset = 4,\
   .spi_host = 1,\
 }
 
-enum freq {
-  F433, F866, F915
-} lora32_freq;
-
 typedef enum {
   B78, B104, B156, B208, B3125, B417, B625, B125, B250, B500
 } bandwidth;
 
-const long long frequencies[3];
+extern const long long frequencies[3];
-const long bandwidths[10];
+extern const long bandwidths[10];
 
 typedef struct lora32_cfg_t lora32_cfg_t;
 
@@ -122,12 +135,22 @@ typedef struct {
   EventGroupHandle_t events;
 } lora32_handle_t;
 
+typedef struct lora32_modem_status_t {
+  unsigned int detected:1;
+  unsigned int synced:1;
+  unsigned int rx:1;
+  unsigned int valid:1;
+  unsigned int clear:1;
+  unsigned int cr:3;
+} lora32_modem_status_t;
+
 typedef struct lora32_cfg_t {
   uint8_t fifoIdx;
   uint8_t channel;
   uint8_t bandwidth;
   uint8_t spreadingFactor;
   uint8_t codingRate;
+  uint8_t version; // to be written on init by the driver
 
   int8_t nss;
   int8_t cipo;
@@ -173,7 +196,7 @@ void lora32_enable_cad(lora32_cfg_t *lora);
 void lora32_disable_fhss(lora32_cfg_t *lora);
 void lora32_toggle_reset(lora32_cfg_t *lora);
 void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
-void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw);
+void lora32_set_bandwidth(lora32_cfg_t *lora, bandwidth bw);
 void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr);
 void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
 uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora);

main/esp32-lora.c

@@ -11,7 +11,7 @@
 #include "driver/gpio.h"
 #include "driver/spi_common.h"
 #include "driver/spi_master.h"
-#include "driver/spi_common_internal.h"
+#include "spi_common_internal.h"
 
 #include "esp32-lora.h"
 
@@ -70,6 +70,17 @@ void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
   xSemaphoreGive(spi_semaphore);
 };
 
+void lora32_update_dio_mapping(lora32_cfg_t *lora, uint8_t reg, uint8_t value, uint8_t shift) {
+  uint8_t regdio1 = lora32_read_reg(lora, reg);
+
+  // clear bits
+  regdio1 &= ~(0b11 << shift);
+  // set new values
+  regdio1 |= (value << shift);
+
+  lora32_write_reg(lora, reg, regdio1);
+}
+
 double lora32_calc_datarate(lora32_cfg_t *lora) {
   double cr = (4.0 / (long)lora->codingRate);
   double sf = pow(2, lora->spreadingFactor);
@@ -79,7 +90,7 @@ double lora32_calc_datarate(lora32_cfg_t *lora) {
   return lora->spreadingFactor * cr / c2 * 1000;
 }
 
-void lora23_set_explicit_header(lora32_cfg_t *lora) {
+void lora32_set_explicit_header(lora32_cfg_t *lora) {
   ESP_LOGD(TAG, "setting explicit header");
 
   lora->implicitHeader = false;
@@ -87,7 +98,7 @@ void lora23_set_explicit_header(lora32_cfg_t *lora) {
   lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE);
 }
 
-void lora23_set_implicit_header(lora32_cfg_t *lora) {
+void lora32_set_implicit_header(lora32_cfg_t *lora) {
   ESP_LOGD(TAG, "setting implicit header");
 
   lora->implicitHeader = true;
@@ -123,9 +134,9 @@ void lora32_enable_tx(lora32_cfg_t *lora) {
   lora32_standby(lora);
 
   if(lora->implicitHeader)
-    lora23_set_implicit_header(lora);
+    lora32_set_implicit_header(lora);
   else
-    lora23_set_explicit_header(lora);
+    lora32_set_explicit_header(lora);
 
   // zero out receive buffer
   lora32_write_reg(lora, REG_FIFO_ADDR_PTR, 0);
@@ -133,9 +144,11 @@ void lora32_enable_tx(lora32_cfg_t *lora) {
 }
 
 void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
+  if(lora == NULL) return;
+
   ESP_ERROR_CHECK(spi_device_acquire_bus(lora->spi, portMAX_DELAY));
 
-  lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE);
+  lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE, DIO0_MODE_SHIFT);
 
   lora32_enable_tx(lora);
 
@@ -257,57 +270,70 @@ void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor) {
     lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER);
   }
 
-  ESP_LOGV(TAG, "lora32_set_spreadfactor: %d", factor);
+  ESP_LOGD(TAG, "lora32_set_spreadfactor: %d", factor);
 
   lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0));
 
   lora->spreadingFactor = factor;
 }
 
-void lora32_enable_single_rx(lora32_cfg_t *lora) {
+lora32_modem_status_t lora32_get_status(lora32_cfg_t *lora) {
-  ESP_LOGD(TAG, "MODE_RX_SINGLE");
+  lora32_modem_status_t modem_status;
+  uint8_t status = lora32_read_reg(lora, REG_MODEM_STATUS);
 
-  if(lora->receive != NULL) {
+  memcpy(&modem_status, &status, 1);
-    lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
+
+  return modem_status;
 }
 
+void lora32_enable_single_rx(lora32_cfg_t *lora) {
+  ESP_LOGD(TAG, "MODE_RX_SINGLE");
   lora32_standby(lora);
 
+  if(lora->receive != NULL) {
+    lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE, DIO0_MODE_SHIFT);
+  }
+
   lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
 }
 
 void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
   ESP_LOGD(TAG, "MODE_RX_CONTINUOUS");
+  lora32_standby(lora);
 
   if(lora->receive != NULL) {
-    lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
+    lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE, DIO0_MODE_SHIFT);
   }
 
-  lora32_standby(lora);
-
   lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
 }
 
 void lora32_enable_cad(lora32_cfg_t *lora) {
-  if((lora->cad_done != NULL) | (lora->cad_detected != NULL)) {
+  lora32_standby(lora);
-    ESP_LOGD(TAG, "Setting DIO0 to CAD Detect");
 
-    lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_CADDET);
+  if(lora->cad_done != NULL) {
+    ESP_LOGV(TAG, "Setting DIO0 to CAD Done");
+    lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO0_MODE_CADDON, DIO0_MODE_SHIFT);
   }
 
-  ESP_LOGD(TAG, "MODE_CAD_DETECT");
+  if(lora->cad_detected != NULL) {
+    ESP_LOGV(TAG, "Setting DIO1 to CAD Detect");
+    lora32_update_dio_mapping(lora, REG_DIO_MAPPING_1, DIO1_MODE_CADDET, DIO1_MODE_SHIFT);
+  }
+
+  ESP_LOGV(TAG, "MODE_CAD_DETECT");
 
   lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_CAD_DETECT);
 }
 
 int16_t lora32_get_rssi(lora32_cfg_t *lora) {
   // TODO support LF output constant of -164
-  return -157 + lora32_read_reg(lora, REG_RSSI_VALUE);
+  return (-157 + lora32_read_reg(lora, REG_RSSI_VALUE)) & 0xffff;
 }
 
 int16_t lora32_get_packet_rssi(lora32_cfg_t *lora) {
   // TODO support LF output constant of -164
-  return -157 + lora32_read_reg(lora, REG_PKT_RSSI_VALUE);
+  return 0x0000 | (-157 + lora32_read_reg(lora, REG_PKT_RSSI_VALUE));
 }
 
 long lora32_get_bandwidth(lora32_cfg_t *lora) {
@@ -336,7 +362,7 @@ void lora32_set_ldo_flag(lora32_cfg_t *lora) {
   lora32_write_reg(lora, REG_MODEM_CONFIG_3, modem_config_3);
 }
 
-void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw) {
+void lora32_set_bandwidth(lora32_cfg_t *lora, bandwidth bw) {
   ESP_LOGD(TAG, "lora32_set_bandwidth: %d", bw);
 
   uint8_t modem_config_1 = lora32_read_reg(lora, REG_MODEM_CONFIG_1);
@@ -390,14 +416,11 @@ static void IRAM_ATTR lora32_dio_task(void *arg) {
     // wait for event over Queue
     if(xQueueReceive(dio_event_queue, (void*)&lora, portMAX_DELAY) != pdPASS) continue;
 
-    // need a better way to log which event and from which config
-    //ESP_LOGI(TAG, "handling DIO0 on GPIO%d", lora->dio0);
-
     spi_device_acquire_bus(lora->spi, portMAX_DELAY);
 
     // read IRQ flags
     uint8_t irqs = lora32_read_reg(lora, REG_IRQ_FLAGS);
-    ESP_LOGD(TAG, "reading irqs: %02X", irqs);
+    ESP_LOGD(TAG, "reading irqs: 0x%02X", irqs);
 
     // clear IRQ flags by writing mask back
     ESP_LOGD(TAG, "clearing irqs");
@@ -484,12 +507,14 @@ uint8_t lora32_spi_init(lora32_cfg_t *lora) {
 }
 
 uint8_t lora32_init(lora32_cfg_t *lora) {
+  esp_log_level_set(TAG, ESP_LOG_DEBUG);
+
   if(spi_semaphore == NULL) {
     spi_semaphore = xSemaphoreCreateMutex();
   }
 
   gpio_config_t io_conf;
-  io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
+  io_conf.intr_type = GPIO_INTR_DISABLE;
   io_conf.mode = GPIO_MODE_OUTPUT;
 
 	io_conf.pin_bit_mask = (1ULL<<lora->reset)|(1ULL<<lora->nss);
@@ -557,9 +582,9 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
   ESP_LOGV(TAG, "lora32_standby");
 
   if(lora->implicitHeader)
-    lora23_set_implicit_header(lora);
+    lora32_set_implicit_header(lora);
   else
-    lora23_set_explicit_header(lora);
+    lora32_set_explicit_header(lora);
 
   // TODO setup shouldn't be based on just receive callback
   if(lora->receive != NULL) {
@@ -575,7 +600,7 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
     if(lora->dio2 > -1)
       pin_bit_mask |= (1 << lora->dio2);
 
-    io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
+    io_conf.intr_type = GPIO_INTR_POSEDGE;
     io_conf.pin_bit_mask = pin_bit_mask;
     io_conf.mode = GPIO_MODE_INPUT;
     io_conf.pull_down_en = 1;