morgan/esp32-lora
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developmen ... dekconfig

3 changed files with 170 additions and 254 deletions
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47
Kconfig Normal file
View file

@ -0,0 +1,47 @@
menuconfig LORA32_ENABLED
bool "LORA32"
default y
help
Select this option to enable LORA32 driver and show the submodule with configuration
config LORA32_NSS_PIN
int "GPIO to handle NSS"
depends on LORA32_ENABLED
default 18
help
GPIO to handle NSS
config LORA32_RESET_PIN
int "GPIO to handle RESET"
depends on LORA32_ENABLED
default 14
help
GPIO to handle RESET
config LORA32_DIO0_PIN
int "GPIO to handle DIO0"
depends on LORA32_ENABLED
default 26
help
GPIO to handle DIO0
config LORA32_MISO_PIN
int "GPIO to handle MISO"
depends on LORA32_ENABLED
default 19
help
GPIO to handle MISO
config LORA32_MOSI_PIN
int "GPIO to handle MOSI"
depends on LORA32_ENABLED
default 27
help
GPIO to handle MOSI
config LORA32_CLK_PIN
int "GPIO to handle CLK"
depends on LORA32_ENABLED
default 5
help
GPIO to handle CLK

68
include/esp32-lora.h
View file

@ -23,13 +23,12 @@
#define REG_IRQ_FLAGS 0x12 #define REG_IRQ_FLAGS 0x12
#define REG_RX_NB_BYTES 0x13 #define REG_RX_NB_BYTES 0x13
#define REG_PKT_RSSI_VALUE 0x1a #define REG_PKT_RSSI_VALUE 0x1a
#define REG_RSSI_VALUE 0x1b #define REG_PKT_SNR_VALUE 0x1b
#define REG_MODEM_CONFIG_1 0x1d #define REG_MODEM_CONFIG_1 0x1d
#define REG_MODEM_CONFIG_2 0x1e #define REG_MODEM_CONFIG_2 0x1e
#define REG_PREAMBLE_MSB 0x20 #define REG_PREAMBLE_MSB 0x20
#define REG_PREAMBLE_LSB 0x21 #define REG_PREAMBLE_LSB 0x21
#define REG_PAYLOAD_LENGTH 0x22 #define REG_PAYLOAD_LENGTH 0x22
#define REG_HOP_PERIOD 0x24
#define REG_MODEM_CONFIG_3 0x26 #define REG_MODEM_CONFIG_3 0x26
#define REG_RSSI_WIDEBAND 0x2c #define REG_RSSI_WIDEBAND 0x2c
#define REG_DETECTION_OPTIMIZE 0x31 #define REG_DETECTION_OPTIMIZE 0x31
@ -78,28 +77,6 @@
#define EV_DIO0 (1 << 0) #define EV_DIO0 (1 << 0)
#define ERR_LOR_VERSION_MISMATCH (01)
#define LORA32_DEFAULT_CONFIG {\
.bandwidth = B250,\
.codingRate = 5,\
.frequency = 915000000,\
.spreadingFactor = 11,\
.preamble = DEFAULT_PREAMBLE,\
.implicitHeader = false,\
.useCRC = false,\
.fifoIdx = 0,\
.copi = -1,\
.cipo = -1,\
.clk = -1,\
.dio0 = -1,\
.dio1 = -1,\
.dio2 = -1,\
.nss = -1,\
.reset = -1,\
.spi_host = 1,\
}
enum freq { enum freq {
F433, F866, F915 F433, F866, F915
} lora32_freq; } lora32_freq;
@ -111,74 +88,53 @@ typedef enum {
const long long frequencies[3]; const long long frequencies[3];
const long bandwidths[10]; const long bandwidths[10];
typedef struct lora32_cfg_t lora32_cfg_t; typedef void (*receiveCallback)(uint8_t size);
typedef void (*txdoneCallback)();
typedef void (*receiveCallback)(lora32_cfg_t *lora, uint8_t size); typedef void (*cadDoneCallback)(bool detected);
typedef void (*txdoneCallback)(lora32_cfg_t *lora); typedef void (*cadDetectedCallback)();
typedef void (*cadDoneCallback)(lora32_cfg_t *lora, bool detected);
typedef void (*cadDetectedCallback)(lora32_cfg_t *lora);
typedef struct { typedef struct {
EventGroupHandle_t events; EventGroupHandle_t events;
} lora32_handle_t; } lora32_handle_t;
typedef struct lora32_cfg_t { typedef struct lora32_cfg_t {
uint8_t nss;
uint8_t dio0;
uint8_t reset;
uint8_t fifoIdx; uint8_t fifoIdx;
uint8_t channel;
uint8_t bandwidth;
uint8_t spreadingFactor;
uint8_t codingRate;
int8_t nss;
int8_t cipo;
int8_t copi;
int8_t clk;
int8_t reset;
int8_t dio0;
int8_t dio1;
int8_t dio2;
int8_t channels[64];
long frequency; long frequency;
uint8_t bandwidth;
uint8_t spreadingFactor;
uint8_t codingRate;
uint16_t preamble; uint16_t preamble;
bool useCRC; bool useCRC;
bool implicitHeader; bool implicitHeader;
bool enableFHSS;
receiveCallback receive; receiveCallback receive;
txdoneCallback tx_done; txdoneCallback tx_done;
cadDoneCallback cad_done; cadDoneCallback cad_done;
cadDetectedCallback cad_detected; cadDetectedCallback cad_detected;
uint8_t spi_host;
spi_device_handle_t spi; spi_device_handle_t spi;
lora32_handle_t handle; lora32_handle_t handle;
} lora32_cfg_t; } lora32_cfg_t;
uint8_t lora32_spi_init(lora32_cfg_t *config); lora32_cfg_t lora32_create();
uint8_t lora32_init(lora32_cfg_t *config); uint8_t lora32_init(lora32_cfg_t *config);
uint8_t lora32_data_available(lora32_cfg_t *lora); uint8_t lora32_data_available(lora32_cfg_t *lora);
int16_t lora32_get_packet_rssi(lora32_cfg_t *lora);
int16_t lora32_get_rssi(lora32_cfg_t *lora);
double lora32_calc_datarate(lora32_cfg_t *lora); double lora32_calc_datarate(lora32_cfg_t *lora);
void lora32_dump_regs(lora32_cfg_t *lora); void lora32_dump_regs(lora32_cfg_t *lora);
void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period);
void lora32_enable_continuous_rx(lora32_cfg_t *lora); void lora32_enable_continuous_rx(lora32_cfg_t *lora);
void lora32_enable_single_rx(lora32_cfg_t *lora);
void lora32_enable_cad(lora32_cfg_t *lora); void lora32_enable_cad(lora32_cfg_t *lora);
void lora32_disable_fhss(lora32_cfg_t *lora);
void lora32_toggle_reset(lora32_cfg_t *lora);
void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len); void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw); void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw);
void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr); void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr);
void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor); void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora);
void lora32_read_data(lora32_cfg_t *lora, uint8_t *data); void lora32_read_data(lora32_cfg_t *lora, uint8_t *data);
void lora32_sleep(lora32_cfg_t *lora);
void lora32_standby(lora32_cfg_t *lora);
#endif // _LORA32_H__ #endif // _LORA32_H__

305
main/esp32-lora.c
View file

@ -2,7 +2,6 @@
#include <math.h> #include <math.h>
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/task.h" #include "freertos/task.h"
#include "freertos/queue.h" #include "freertos/queue.h"
@ -11,13 +10,16 @@
#include "driver/gpio.h" #include "driver/gpio.h"
#include "driver/spi_common.h" #include "driver/spi_common.h"
#include "driver/spi_master.h" #include "driver/spi_master.h"
#include "driver/spi_common_internal.h"
#include "esp32-lora.h" #include "esp32-lora.h"
#define READ_REG 0x7F #define READ_REG 0x7F
#define WRITE_REG 0x80 #define WRITE_REG 0x80
#define PIN_NUM_MISO CONFIG_LORA32_MISO_PIN
#define PIN_NUM_MOSI CONFIG_LORA32_MOSI_PIN
#define PIN_NUM_CLK CONFIG_LORA32_CLK_PIN
#define PA_OUTPUT_RFO_PIN 0 #define PA_OUTPUT_RFO_PIN 0
#define PA_OUTPUT_PA_BOOST_PIN 1 #define PA_OUTPUT_PA_BOOST_PIN 1
@ -26,13 +28,45 @@ const long bandwidths[] = { 7.8e3, 10.4e3, 15.6e3, 20.8e3, 31.25e3, 41.7e3, 62.5
const char *TAG = "LoRa32"; const char *TAG = "LoRa32";
static QueueHandle_t dio_event_queue; lora32_cfg_t lora32_create() {
static TaskHandle_t dio_task_handle; static spi_device_handle_t spi;
static SemaphoreHandle_t spi_semaphore;
return (lora32_cfg_t){
.bandwidth = B125,
.codingRate = DEFAULT_CR,
.dio0 = CONFIG_LORA32_DIO0_PIN,
.implicitHeader = false,
.nss = CONFIG_LORA32_NSS_PIN,
.reset = CONFIG_LORA32_RESET_PIN,
.frequency = 915000000,
.preamble = DEFAULT_PREAMBLE,
.spreadingFactor = DEFAULT_SF,
.spi = spi,
.receive = NULL,
.useCRC = false,
.fifoIdx = 0
};
}
void lora32_send_cmd(lora32_cfg_t lora, uint8_t cmd, uint8_t value, uint8_t len, uint8_t *rx_buffer) {
uint8_t tx_buffer[2];
tx_buffer[0] = cmd;
tx_buffer[1] = value;
spi_transaction_t t;
memset(&t, 0, sizeof(t));
t.length = 8 * len;
t.rxlength = 8 * len;
t.tx_buffer = &tx_buffer;
t.rx_buffer = rx_buffer;
ESP_ERROR_CHECK(spi_device_transmit(lora.spi, &t));
//ESP_LOGI(TAG, "send_cmd rx_data: 0x%2X 0x%2X", rx_buffer[0], rx_buffer[1]);
}
uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) { uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
xSemaphoreTake(spi_semaphore, portMAX_DELAY);
spi_transaction_t t; spi_transaction_t t;
memset(&t, 0, sizeof(spi_transaction_t)); memset(&t, 0, sizeof(spi_transaction_t));
@ -45,14 +79,10 @@ uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
ESP_LOGV(TAG, "<%2X<%2X", address, t.rx_data[1]); ESP_LOGV(TAG, "<%2X<%2X", address, t.rx_data[1]);
xSemaphoreGive(spi_semaphore);
return t.rx_data[1]; return t.rx_data[1];
} }
void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) { void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
xSemaphoreTake(spi_semaphore, portMAX_DELAY);
spi_device_handle_t spi = lora->spi; spi_device_handle_t spi = lora->spi;
spi_transaction_t t; spi_transaction_t t;
@ -66,61 +96,43 @@ void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
t.tx_data[1] = value; t.tx_data[1] = value;
ESP_ERROR_CHECK(spi_device_transmit(spi, &t)); ESP_ERROR_CHECK(spi_device_transmit(spi, &t));
xSemaphoreGive(spi_semaphore);
}; };
double lora32_calc_datarate(lora32_cfg_t *lora) { double lora32_calc_datarate(lora32_cfg_t *lora) {
double cr = (4.0 / (long)lora->codingRate); double cr = (4.0 / (long)lora->codingRate);
double sf = pow(2, lora->spreadingFactor); double sf = pow(2, lora->spreadingFactor);
double c2 = sf / bandwidths[lora->bandwidth]; double c2 = sf / bandwidths[lora->bandwidth];
ESP_LOGD(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2); ESP_LOGI(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2);
return lora->spreadingFactor * cr / c2 * 1000; return lora->spreadingFactor * cr / c2 * 1000;
} }
void lora23_set_explicit_header(lora32_cfg_t *lora) { void lora23_set_explicit_header(lora32_cfg_t *lora) {
ESP_LOGD(TAG, "setting explicit header");
lora->implicitHeader = false; lora->implicitHeader = false;
lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE); lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE);
} }
void lora23_set_implicit_header(lora32_cfg_t *lora) { void lora23_set_implicit_header(lora32_cfg_t *lora) {
ESP_LOGD(TAG, "setting implicit header");
lora->implicitHeader = true; lora->implicitHeader = true;
lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) | 0x01); lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) | 0x01);
} }
void lora32_standby(lora32_cfg_t *lora) { void lora32_idle(lora32_cfg_t *lora) {
ESP_LOGV(TAG, "MODE_STANDBY"); ESP_LOGD(TAG, "MODE_STANDBY");
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STANDBY); lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STANDBY);
} }
void lora32_sleep(lora32_cfg_t *lora) { void lora32_sleep(lora32_cfg_t *lora) {
ESP_LOGV(TAG, "MODE_SLEEP"); ESP_LOGD(TAG, "MODE_SLEEP");
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP); lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
} }
void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period) {
lora->enableFHSS = true;
lora32_write_reg(lora, REG_HOP_PERIOD, period);
}
void lora32_disable_fhss(lora32_cfg_t *lora) {
lora->enableFHSS = false;
lora32_write_reg(lora, REG_HOP_PERIOD, 0);
}
void lora32_enable_tx(lora32_cfg_t *lora) { void lora32_enable_tx(lora32_cfg_t *lora) {
lora32_standby(lora); lora32_idle(lora);
if(lora->implicitHeader) if(lora->implicitHeader)
lora23_set_implicit_header(lora); lora23_set_implicit_header(lora);
@ -133,8 +145,6 @@ void lora32_enable_tx(lora32_cfg_t *lora) {
} }
void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) { void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
ESP_ERROR_CHECK(spi_device_acquire_bus(lora->spi, portMAX_DELAY));
lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE); lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE);
lora32_enable_tx(lora); lora32_enable_tx(lora);
@ -146,17 +156,15 @@ void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
lora32_write_reg(lora, REG_PAYLOAD_LENGTH, len); lora32_write_reg(lora, REG_PAYLOAD_LENGTH, len);
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX); lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
spi_device_release_bus(lora->spi);
} }
void lora32_set_frequency(lora32_cfg_t *lora, long frequency) { void lora32_set_frequency(lora32_cfg_t *lora, long frequency) {
ESP_LOGD(TAG, "lora32_set_frequency: %lu", frequency); ESP_LOGI(TAG, "lora32_set_frequency: %lu", frequency);
uint64_t frf = ((uint64_t)frequency << 19) / 32000000; uint64_t frf = ((uint64_t)frequency << 19) / 32000000;
ESP_LOGD(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16)); ESP_LOGI(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
ESP_LOGD(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8)); ESP_LOGI(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
ESP_LOGD(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0)); ESP_LOGI(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16)); lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16));
lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8)); lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8));
@ -194,7 +202,7 @@ void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2)); lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2));
} }
ESP_LOGD(TAG, "set_tx_power(%d, %d)", level, output); ESP_LOGI(TAG, "set_tx_power(%d, %d)", level, output);
ESP_LOGD(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(lora, REG_PA_CONFIG)); ESP_LOGD(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(lora, REG_PA_CONFIG));
} }
@ -231,7 +239,7 @@ void lora32_dump_regs(lora32_cfg_t *lora) {
void lora32_toggle_reset(lora32_cfg_t *config) { void lora32_toggle_reset(lora32_cfg_t *config) {
// toggle reset (L/H) // toggle reset (L/H)
ESP_LOGD(TAG, "Toggling reset pin %d", config->reset); ESP_LOGI(TAG, "Toggling reset pin %d", config->reset);
gpio_set_level(config->reset, 0); gpio_set_level(config->reset, 0);
vTaskDelay(100 / portTICK_PERIOD_MS); // requires 100us vTaskDelay(100 / portTICK_PERIOD_MS); // requires 100us
@ -240,7 +248,7 @@ void lora32_toggle_reset(lora32_cfg_t *config) {
vTaskDelay(100 / portTICK_PERIOD_MS); // 5ms before available vTaskDelay(100 / portTICK_PERIOD_MS); // 5ms before available
} }
uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora) { uint8_t lora32_get_spreadingfactor(lora32_cfg_t *lora) {
return (lora32_read_reg(lora, REG_MODEM_CONFIG_2) >> 4); return (lora32_read_reg(lora, REG_MODEM_CONFIG_2) >> 4);
} }
@ -257,23 +265,9 @@ void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor) {
lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER); lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER);
} }
ESP_LOGV(TAG, "lora32_set_spreadfactor: %d", factor); ESP_LOGI(TAG, "lora32_set_spreadfactor: %d", factor);
lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0)); lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0));
lora->spreadingFactor = factor;
}
void lora32_enable_single_rx(lora32_cfg_t *lora) {
ESP_LOGD(TAG, "MODE_RX_SINGLE");
if(lora->receive != NULL) {
lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
}
lora32_standby(lora);
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
} }
void lora32_enable_continuous_rx(lora32_cfg_t *lora) { void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
@ -283,8 +277,6 @@ void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE); lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
} }
lora32_standby(lora);
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS); lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
} }
@ -300,44 +292,34 @@ void lora32_enable_cad(lora32_cfg_t *lora) {
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_CAD_DETECT); lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_CAD_DETECT);
} }
int16_t lora32_get_rssi(lora32_cfg_t *lora) {
// TODO support LF output constant of -164
return -157 + lora32_read_reg(lora, REG_RSSI_VALUE);
}
int16_t lora32_get_packet_rssi(lora32_cfg_t *lora) {
// TODO support LF output constant of -164
return -157 + lora32_read_reg(lora, REG_PKT_RSSI_VALUE);
}
long lora32_get_bandwidth(lora32_cfg_t *lora) { long lora32_get_bandwidth(lora32_cfg_t *lora) {
uint8_t bw = (lora32_read_reg(lora, REG_MODEM_CONFIG_1) >> 4); uint8_t bw = (lora32_read_reg(lora, REG_MODEM_CONFIG_1) >> 4);
ESP_LOGV(TAG, "lora32_get_bandwidth: %d", bw); ESP_LOGI(TAG, "lora32_get_bandwidth: %d", bw);
if(bw > 9) return -1; if(bw > 9) return -1;
ESP_LOGD(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]); ESP_LOGI(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]);
return bandwidths[bw]; return bandwidths[bw];
} }
void lora32_set_ldo_flag(lora32_cfg_t *lora) { void lora32_set_ldo_flag(lora32_cfg_t *lora) {
long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadfactor(lora))); long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadingfactor(lora)));
ESP_LOGD(TAG, "symbolDuration: %ld", symbolDuration); ESP_LOGI(TAG, "symbolDuration: %ld", symbolDuration);
bool ldoOn = symbolDuration > 16; bool ldoOn = symbolDuration > 16;
ESP_LOGD(TAG, "ldoOn: %d", ldoOn); ESP_LOGI(TAG, "ldoOn: %d", ldoOn);
uint8_t modem_config_3 = lora32_read_reg(lora, REG_MODEM_CONFIG_3); uint8_t modem_config_3 = lora32_read_reg(lora, REG_MODEM_CONFIG_3);
ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3); ESP_LOGI(TAG, "modem_config_3: %d", modem_config_3);
modem_config_3 |= ldoOn << 3; modem_config_3 |= ldoOn << 3;
ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3); ESP_LOGI(TAG, "modem_config_3: %d", modem_config_3);
lora32_write_reg(lora, REG_MODEM_CONFIG_3, modem_config_3); lora32_write_reg(lora, REG_MODEM_CONFIG_3, modem_config_3);
} }
void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw) { void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw) {
ESP_LOGD(TAG, "lora32_set_bandwidth: %d", bw); ESP_LOGI(TAG, "lora32_set_bandwidth: %d", bw);
uint8_t modem_config_1 = lora32_read_reg(lora, REG_MODEM_CONFIG_1); uint8_t modem_config_1 = lora32_read_reg(lora, REG_MODEM_CONFIG_1);
lora32_write_reg(lora, REG_MODEM_CONFIG_1, (modem_config_1 & 0x0F) | (bw << 4)); lora32_write_reg(lora, REG_MODEM_CONFIG_1, (modem_config_1 & 0x0F) | (bw << 4));
@ -351,7 +333,7 @@ void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr) {
cr = cr - 4; cr = cr - 4;
ESP_LOGD(TAG, "lora32_set_coding_rate: %d", cr + 4); ESP_LOGI(TAG, "lora32_set_coding_rate: %d", cr + 4);
lora32_write_reg(lora, REG_MODEM_CONFIG_1, (lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xF1) | (cr << 1)); lora32_write_reg(lora, REG_MODEM_CONFIG_1, (lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xF1) | (cr << 1));
} }
@ -365,7 +347,7 @@ void lora32_set_lna(lora32_cfg_t *lora, uint8_t gain) {
uint8_t lna = lora32_read_reg(lora, REG_LNA); uint8_t lna = lora32_read_reg(lora, REG_LNA);
lora32_write_reg(lora, REG_LNA, lna | gain); lora32_write_reg(lora, REG_LNA, lna | gain);
ESP_LOGD(TAG, "set lna: 0x%2X", lna | gain); ESP_LOGI(TAG, "set lna: 0x%2X", lna | gain);
} }
static void lora32_handle_receive(lora32_cfg_t *lora) { static void lora32_handle_receive(lora32_cfg_t *lora) {
@ -378,40 +360,35 @@ static void lora32_handle_receive(lora32_cfg_t *lora) {
lora32_write_reg(lora, REG_FIFO_ADDR_PTR, fifo_addr); lora32_write_reg(lora, REG_FIFO_ADDR_PTR, fifo_addr);
lora->receive(lora, len); lora->receive(len);
} }
static void IRAM_ATTR lora32_dio_task(void *arg) { static void IRAM_ATTR lora32_dio0_task(void *arg) {
// allocate lora32_cfg_t to receive config from Queu lora32_cfg_t *lora = (lora32_cfg_t*)arg;
lora32_cfg_t *lora = malloc(sizeof(lora32_cfg_t)); ESP_LOGD(TAG, "starting DIO0 handler task");
ESP_LOGD(TAG, "starting DIO handler task");
while(1) { while(1) {
// wait for event over Queue EventBits_t evbits = xEventGroupWaitBits(lora->handle.events, EV_DIO0, pdTRUE, pdFALSE, 5000 / portTICK_PERIOD_MS);
if(xQueueReceive(dio_event_queue, (void*)&lora, portMAX_DELAY) != pdPASS) continue;
// need a better way to log which event and from which config // timed out, loop and continue to wait
//ESP_LOGI(TAG, "handling DIO0 on GPIO%d", lora->dio0); if(evbits == 0) continue;
spi_device_acquire_bus(lora->spi, portMAX_DELAY); ESP_LOGD(TAG, "handling DIO0");
// read IRQ flags // read IRQ flags
uint8_t irqs = lora32_read_reg(lora, REG_IRQ_FLAGS); uint8_t irqs = lora32_read_reg(lora, REG_IRQ_FLAGS);
ESP_LOGD(TAG, "reading irqs: %02X", irqs); ESP_LOGD(TAG, "reading irqs: %02X", irqs);
// clear IRQ flags
// clear IRQ flags by writing mask back
ESP_LOGD(TAG, "clearing irqs"); ESP_LOGD(TAG, "clearing irqs");
lora32_write_reg(lora, REG_IRQ_FLAGS, irqs); lora32_write_reg(lora, REG_IRQ_FLAGS, irqs);
spi_device_release_bus(lora->spi);
// TODO handle header validation // TODO handle header validation
if((irqs & IRQ_RX_DONE) == IRQ_RX_DONE) { if((irqs & IRQ_RX_DONE) == IRQ_RX_DONE) {
lora32_handle_receive(lora); lora32_handle_receive(lora);
} }
if((irqs & IRQ_TX_DONE) == IRQ_TX_DONE) { if((irqs & IRQ_TX_DONE) == IRQ_TX_DONE) {
if(lora->tx_done != NULL) lora->tx_done(lora); if(lora->tx_done != NULL) lora->tx_done();
} }
bool cad_detected = false; bool cad_detected = false;
@ -421,28 +398,13 @@ static void IRAM_ATTR lora32_dio_task(void *arg) {
cad_detected = true; cad_detected = true;
// no need for arg, cad_detected callback is always presummed true // no need for arg, cad_detected callback is always presummed true
if(lora->cad_detected != NULL) lora->cad_detected(lora); if(lora->cad_detected != NULL) lora->cad_detected();
} }
if((irqs & IRQ_CAD_DONE) == IRQ_CAD_DONE) { if((irqs & IRQ_CAD_DONE) == IRQ_CAD_DONE) {
// cad_done gets true/false from above, when activity is detected // cad_done gets true/false from above, when activity is detected
// these *should* fire at the same time, defaults to false // these *should* fire at the same time, defaults to false
if(lora->cad_done != NULL) lora->cad_done(lora, cad_detected); if(lora->cad_done != NULL) lora->cad_done(cad_detected);
}
if((irqs & IRQ_FHSS_CHANGE) == IRQ_FHSS_CHANGE) {
ESP_LOGD(TAG, "switching channel %d: %d", lora->channel, lora->channels[lora->channel]);
if(lora->channel == 0 && lora->channels[lora->channel] == 0) continue;
if(lora->channels[lora->channel] == 0) {
ESP_LOGD(TAG, "reseting to channel 0");
lora->channel = 0;
}
lora32_set_frequency(lora, lora->frequency + (lora->channels[lora->channel] * bandwidths[lora->bandwidth]));
lora->channel++;
} }
} }
} }
@ -451,43 +413,20 @@ void lora32_read_data(lora32_cfg_t *lora, uint8_t *data) {
uint8_t i = 0; uint8_t i = 0;
uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES)); uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
ESP_LOGD(TAG, "Reading %d bytes", len); ESP_LOGI(TAG, "Reading %d bytes", len);
for(i = 0; i < len; i++) { for(i = 0; i < len; i++) {
data[i] = lora32_read_reg(lora, REG_FIFO); data[i] = lora32_read_reg(lora, REG_FIFO);
} }
} }
static void IRAM_ATTR lora32_on_dio(void *arg) { static void IRAM_ATTR lora32_on_dio0(void *arg) {
xQueueSendFromISR(dio_event_queue, (void*)&arg, pdFALSE); BaseType_t woken = pdFALSE;
}
uint8_t lora32_spi_init(lora32_cfg_t *lora) { xEventGroupSetBitsFromISR(((lora32_cfg_t*)arg)->handle.events, EV_DIO0, &woken);
ESP_LOGD(TAG, "Initializing SPI bus");
esp_err_t err = ESP_OK;
spi_bus_config_t buscfg = {
.miso_io_num = lora->cipo,
.mosi_io_num = lora->copi,
.sclk_io_num = lora->clk,
.quadwp_io_num = -1,
.quadhd_io_num = -1
};
if(spi_bus_get_attr(lora->spi_host) == NULL) {
// 2 should be SPI_DMA_CH_AUTO ??? but it doesn't seem to be defined
err = spi_bus_initialize(lora->spi_host, &buscfg, 2);
}
return err;
} }
uint8_t lora32_init(lora32_cfg_t *lora) { uint8_t lora32_init(lora32_cfg_t *lora) {
if(spi_semaphore == NULL) {
spi_semaphore = xSemaphoreCreateMutex();
}
gpio_config_t io_conf; gpio_config_t io_conf;
io_conf.intr_type = GPIO_PIN_INTR_DISABLE; io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.mode = GPIO_MODE_OUTPUT; io_conf.mode = GPIO_MODE_OUTPUT;
@ -499,12 +438,24 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
lora32_toggle_reset(lora); lora32_toggle_reset(lora);
// set NSS high // set NSS high
ESP_LOGD(TAG, "Bringing NSS high: %d", lora->nss); ESP_LOGI(TAG, "Bringing NSS high: %d", lora->nss);
gpio_set_level(lora->nss, 1); gpio_set_level(lora->nss, 1);
vTaskDelay(10 / portTICK_PERIOD_MS); vTaskDelay(10 / portTICK_PERIOD_MS);
// SPI device setup // init spi
ESP_LOGI(TAG, "Initializing SPI bus");
// TODO fix this awkward log along with pin assignments in general
ESP_LOGI(TAG, "\n MISO: %d\nMOSI: %d\nCLK: %d\nNSS: %d", PIN_NUM_MISO, PIN_NUM_MOSI, PIN_NUM_CLK, lora->nss);
spi_bus_config_t buscfg = {
.miso_io_num = PIN_NUM_MISO,
.mosi_io_num = PIN_NUM_MOSI,
.sclk_io_num = PIN_NUM_CLK,
.quadwp_io_num = -1,
.quadhd_io_num = -1
};
spi_device_interface_config_t devcfg = { spi_device_interface_config_t devcfg = {
.clock_speed_hz = 8E6, .clock_speed_hz = 8E6,
.flags = 0, .flags = 0,
@ -513,26 +464,19 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
.queue_size = 7, .queue_size = 7,
}; };
ESP_ERROR_CHECK(spi_bus_add_device(lora->spi_host, &devcfg, &lora->spi)); ESP_ERROR_CHECK(spi_bus_initialize(HSPI_HOST, &buscfg, 0));
ESP_ERROR_CHECK(spi_bus_add_device(HSPI_HOST, &devcfg, &lora->spi));
// initialize event groups // initialize event groups
lora->handle.events = xEventGroupCreate(); lora->handle.events = xEventGroupCreate();
uint8_t version = lora32_read_reg(lora, REG_VERSION); uint8_t version = lora32_read_reg(lora, REG_VERSION);
ESP_LOGD(TAG, "lora32_get_id() == 0x%2X", version); ESP_LOGD(TAG, "lora32_get_id() == 0x%2X", version);
assert(version == 0x12);
lora->version = version;
// if ID does not match, something is likely wrong on the SPI bus
if(version != 0x12) {
ESP_LOGE(TAG, "REG_VERSION returned incorrectly. Expected 0x12 got 0x%02X", version);
return ERR_LOR_VERSION_MISMATCH;
}
// TODO: confirm this is happening. Before/after power measurements? // TODO: confirm this is happening. Before/after power measurements?
lora32_sleep(lora); lora32_sleep(lora);
ESP_LOGV(TAG, "lora32_sleep"); ESP_LOGI(TAG, "lora32_sleep");
// TODO: VERIFY // TODO: VERIFY
lora32_set_frequency(lora, lora->frequency); lora32_set_frequency(lora, lora->frequency);
@ -542,7 +486,7 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
lora32_write_reg(lora, REG_FIFO_TX_BASE_ADDR, 0x00); lora32_write_reg(lora, REG_FIFO_TX_BASE_ADDR, 0x00);
lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00); lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00);
ESP_LOGV(TAG, "clear rx/tx fifos"); ESP_LOGI(TAG, "clear rx/tx fifos");
lora32_set_lna(lora, 0x03); lora32_set_lna(lora, 0x03);
@ -551,61 +495,30 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
// TODO make based on config // TODO make based on config
lora32_set_tx_power(lora, 17, PA_OUTPUT_PA_BOOST_PIN); lora32_set_tx_power(lora, 17, PA_OUTPUT_PA_BOOST_PIN);
ESP_LOGV(TAG, "lora32_set_tx_power"); ESP_LOGI(TAG, "lora32_set_tx_power");
lora32_standby(lora); lora32_idle(lora);
ESP_LOGV(TAG, "lora32_standby"); ESP_LOGI(TAG, "lora32_idle");
if(lora->implicitHeader)
lora23_set_implicit_header(lora);
else
lora23_set_explicit_header(lora);
// TODO setup shouldn't be based on just receive callback // TODO setup shouldn't be based on just receive callback
if(lora->receive != NULL) { if(lora->receive != NULL) {
ESP_LOGV(TAG, "Setting GPIO Interrupt"); ESP_LOGI(TAG, "Setting callback handler");
// TODO check at least one DIOx pin is not NULL
uint64_t pin_bit_mask = 0;
if(lora->dio0 > -1)
pin_bit_mask |= (1 << lora->dio0);
if(lora->dio1 > -1)
pin_bit_mask |= (1 << lora->dio1);
if(lora->dio2 > -1)
pin_bit_mask |= (1 << lora->dio2);
io_conf.intr_type = GPIO_PIN_INTR_POSEDGE; io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
io_conf.pin_bit_mask = pin_bit_mask; io_conf.pin_bit_mask = (1ULL << CONFIG_LORA32_DIO0_PIN);
io_conf.mode = GPIO_MODE_INPUT; io_conf.mode = GPIO_MODE_INPUT;
io_conf.pull_down_en = 1; io_conf.pull_down_en = 0;
io_conf.pull_up_en = 0; io_conf.pull_up_en = 0;
gpio_config(&io_conf); gpio_config(&io_conf);
// the DIO interrupt handling for every device is done from one task gpio_set_intr_type(CONFIG_LORA32_DIO0_PIN, GPIO_INTR_POSEDGE);
if(dio_task_handle == NULL) {
ESP_LOGV(TAG, "Setting callback handler and ISR service");
// enable global ISR service
gpio_install_isr_service(0); gpio_install_isr_service(0);
dio_event_queue = xQueueCreate(10, sizeof(lora32_cfg_t *)); gpio_isr_handler_add(CONFIG_LORA32_DIO0_PIN, lora32_on_dio0, (void*)lora);
// this should probably be high priority // this should probably be high priority
xTaskCreate(&lora32_dio_task, "lora32_dio_task", 4096, NULL, 6, &dio_task_handle); xTaskCreate(&lora32_dio0_task, "lora32_dio0_task", 14048, (void*)lora, 6, NULL);
} }
// add ISR handler to the global service started (once) above return 1;
ESP_LOGV(TAG, "Installing ISR handler for GPIO%d", lora->dio0);
if(lora->dio0 > -1)
gpio_isr_handler_add(lora->dio0, lora32_on_dio, (void*)lora);
if(lora->dio1 > -1)
gpio_isr_handler_add(lora->dio1, lora32_on_dio, (void*)lora);
if(lora->dio2 > -1)
gpio_isr_handler_add(lora->dio2, lora32_on_dio, (void*)lora);
}
return ESP_OK;
}; };