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dekconfig
3 changed files with 170 additions and 254 deletions
47
Kconfig
Normal file
47
Kconfig
Normal file
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@ -0,0 +1,47 @@
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menuconfig LORA32_ENABLED
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bool "LORA32"
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default y
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help
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Select this option to enable LORA32 driver and show the submodule with configuration
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config LORA32_NSS_PIN
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int "GPIO to handle NSS"
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depends on LORA32_ENABLED
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default 18
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help
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GPIO to handle NSS
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config LORA32_RESET_PIN
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int "GPIO to handle RESET"
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depends on LORA32_ENABLED
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default 14
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help
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GPIO to handle RESET
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config LORA32_DIO0_PIN
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int "GPIO to handle DIO0"
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depends on LORA32_ENABLED
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default 26
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help
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GPIO to handle DIO0
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config LORA32_MISO_PIN
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int "GPIO to handle MISO"
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depends on LORA32_ENABLED
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default 19
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help
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GPIO to handle MISO
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config LORA32_MOSI_PIN
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int "GPIO to handle MOSI"
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depends on LORA32_ENABLED
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default 27
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help
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GPIO to handle MOSI
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config LORA32_CLK_PIN
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int "GPIO to handle CLK"
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depends on LORA32_ENABLED
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default 5
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help
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GPIO to handle CLK
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@ -23,13 +23,12 @@
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#define REG_IRQ_FLAGS 0x12
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#define REG_RX_NB_BYTES 0x13
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#define REG_PKT_RSSI_VALUE 0x1a
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#define REG_RSSI_VALUE 0x1b
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#define REG_PKT_SNR_VALUE 0x1b
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#define REG_MODEM_CONFIG_1 0x1d
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#define REG_MODEM_CONFIG_2 0x1e
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#define REG_PREAMBLE_MSB 0x20
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#define REG_PREAMBLE_LSB 0x21
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_HOP_PERIOD 0x24
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#define REG_MODEM_CONFIG_3 0x26
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#define REG_RSSI_WIDEBAND 0x2c
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#define REG_DETECTION_OPTIMIZE 0x31
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@ -78,28 +77,6 @@
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#define EV_DIO0 (1 << 0)
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#define ERR_LOR_VERSION_MISMATCH (01)
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#define LORA32_DEFAULT_CONFIG {\
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.bandwidth = B250,\
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.codingRate = 5,\
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.frequency = 915000000,\
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.spreadingFactor = 11,\
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.preamble = DEFAULT_PREAMBLE,\
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.implicitHeader = false,\
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.useCRC = false,\
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.fifoIdx = 0,\
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.copi = -1,\
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.cipo = -1,\
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.clk = -1,\
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.dio0 = -1,\
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.dio1 = -1,\
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.dio2 = -1,\
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.nss = -1,\
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.reset = -1,\
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.spi_host = 1,\
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}
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enum freq {
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F433, F866, F915
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} lora32_freq;
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@ -111,74 +88,53 @@ typedef enum {
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const long long frequencies[3];
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const long bandwidths[10];
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typedef struct lora32_cfg_t lora32_cfg_t;
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typedef void (*receiveCallback)(lora32_cfg_t *lora, uint8_t size);
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typedef void (*txdoneCallback)(lora32_cfg_t *lora);
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typedef void (*cadDoneCallback)(lora32_cfg_t *lora, bool detected);
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typedef void (*cadDetectedCallback)(lora32_cfg_t *lora);
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typedef void (*receiveCallback)(uint8_t size);
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typedef void (*txdoneCallback)();
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typedef void (*cadDoneCallback)(bool detected);
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typedef void (*cadDetectedCallback)();
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typedef struct {
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EventGroupHandle_t events;
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} lora32_handle_t;
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typedef struct lora32_cfg_t {
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uint8_t nss;
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uint8_t dio0;
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uint8_t reset;
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uint8_t fifoIdx;
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uint8_t channel;
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uint8_t bandwidth;
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uint8_t spreadingFactor;
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uint8_t codingRate;
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int8_t nss;
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int8_t cipo;
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int8_t copi;
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int8_t clk;
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int8_t reset;
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int8_t dio0;
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int8_t dio1;
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int8_t dio2;
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int8_t channels[64];
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long frequency;
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uint8_t bandwidth;
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uint8_t spreadingFactor;
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uint8_t codingRate;
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uint16_t preamble;
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bool useCRC;
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bool implicitHeader;
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bool enableFHSS;
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receiveCallback receive;
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txdoneCallback tx_done;
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cadDoneCallback cad_done;
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cadDetectedCallback cad_detected;
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uint8_t spi_host;
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spi_device_handle_t spi;
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lora32_handle_t handle;
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} lora32_cfg_t;
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uint8_t lora32_spi_init(lora32_cfg_t *config);
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lora32_cfg_t lora32_create();
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uint8_t lora32_init(lora32_cfg_t *config);
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uint8_t lora32_data_available(lora32_cfg_t *lora);
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int16_t lora32_get_packet_rssi(lora32_cfg_t *lora);
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int16_t lora32_get_rssi(lora32_cfg_t *lora);
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double lora32_calc_datarate(lora32_cfg_t *lora);
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void lora32_dump_regs(lora32_cfg_t *lora);
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void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period);
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void lora32_enable_continuous_rx(lora32_cfg_t *lora);
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void lora32_enable_single_rx(lora32_cfg_t *lora);
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void lora32_enable_cad(lora32_cfg_t *lora);
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void lora32_disable_fhss(lora32_cfg_t *lora);
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void lora32_toggle_reset(lora32_cfg_t *lora);
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void lora32_send(lora32_cfg_t *config, uint8_t *data, uint8_t len);
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void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw);
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void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr);
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void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor);
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uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora);
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void lora32_read_data(lora32_cfg_t *lora, uint8_t *data);
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void lora32_sleep(lora32_cfg_t *lora);
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void lora32_standby(lora32_cfg_t *lora);
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#endif // _LORA32_H__
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@ -2,7 +2,6 @@
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#include <math.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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@ -11,13 +10,16 @@
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#include "driver/gpio.h"
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#include "driver/spi_common.h"
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#include "driver/spi_master.h"
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#include "driver/spi_common_internal.h"
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#include "esp32-lora.h"
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#define READ_REG 0x7F
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#define WRITE_REG 0x80
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#define PIN_NUM_MISO CONFIG_LORA32_MISO_PIN
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#define PIN_NUM_MOSI CONFIG_LORA32_MOSI_PIN
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#define PIN_NUM_CLK CONFIG_LORA32_CLK_PIN
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#define PA_OUTPUT_RFO_PIN 0
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#define PA_OUTPUT_PA_BOOST_PIN 1
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@ -26,13 +28,45 @@ const long bandwidths[] = { 7.8e3, 10.4e3, 15.6e3, 20.8e3, 31.25e3, 41.7e3, 62.5
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const char *TAG = "LoRa32";
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static QueueHandle_t dio_event_queue;
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static TaskHandle_t dio_task_handle;
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static SemaphoreHandle_t spi_semaphore;
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lora32_cfg_t lora32_create() {
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static spi_device_handle_t spi;
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return (lora32_cfg_t){
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.bandwidth = B125,
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.codingRate = DEFAULT_CR,
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.dio0 = CONFIG_LORA32_DIO0_PIN,
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.implicitHeader = false,
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.nss = CONFIG_LORA32_NSS_PIN,
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.reset = CONFIG_LORA32_RESET_PIN,
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.frequency = 915000000,
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.preamble = DEFAULT_PREAMBLE,
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.spreadingFactor = DEFAULT_SF,
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.spi = spi,
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.receive = NULL,
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.useCRC = false,
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.fifoIdx = 0
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};
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}
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void lora32_send_cmd(lora32_cfg_t lora, uint8_t cmd, uint8_t value, uint8_t len, uint8_t *rx_buffer) {
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uint8_t tx_buffer[2];
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tx_buffer[0] = cmd;
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tx_buffer[1] = value;
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spi_transaction_t t;
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memset(&t, 0, sizeof(t));
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t.length = 8 * len;
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t.rxlength = 8 * len;
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t.tx_buffer = &tx_buffer;
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t.rx_buffer = rx_buffer;
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ESP_ERROR_CHECK(spi_device_transmit(lora.spi, &t));
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//ESP_LOGI(TAG, "send_cmd rx_data: 0x%2X 0x%2X", rx_buffer[0], rx_buffer[1]);
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}
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uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
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xSemaphoreTake(spi_semaphore, portMAX_DELAY);
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spi_transaction_t t;
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memset(&t, 0, sizeof(spi_transaction_t));
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@ -45,14 +79,10 @@ uint8_t lora32_read_reg(lora32_cfg_t *lora, uint8_t address) {
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ESP_LOGV(TAG, "<%2X<%2X", address, t.rx_data[1]);
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xSemaphoreGive(spi_semaphore);
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return t.rx_data[1];
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}
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void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
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xSemaphoreTake(spi_semaphore, portMAX_DELAY);
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spi_device_handle_t spi = lora->spi;
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spi_transaction_t t;
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@ -66,61 +96,43 @@ void lora32_write_reg(lora32_cfg_t *lora, uint8_t address, uint8_t value) {
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t.tx_data[1] = value;
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ESP_ERROR_CHECK(spi_device_transmit(spi, &t));
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xSemaphoreGive(spi_semaphore);
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};
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double lora32_calc_datarate(lora32_cfg_t *lora) {
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double cr = (4.0 / (long)lora->codingRate);
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double sf = pow(2, lora->spreadingFactor);
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double c2 = sf / bandwidths[lora->bandwidth];
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ESP_LOGD(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2);
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ESP_LOGI(TAG, "codingRate: %d cr: %f sf: %f c2: %f", lora->codingRate, cr, sf, c2);
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return lora->spreadingFactor * cr / c2 * 1000;
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}
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void lora23_set_explicit_header(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "setting explicit header");
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lora->implicitHeader = false;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xFE);
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}
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void lora23_set_implicit_header(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "setting implicit header");
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lora->implicitHeader = true;
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lora32_write_reg(lora, REG_MODEM_CONFIG_1, lora32_read_reg(lora, REG_MODEM_CONFIG_1) | 0x01);
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}
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void lora32_standby(lora32_cfg_t *lora) {
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ESP_LOGV(TAG, "MODE_STANDBY");
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void lora32_idle(lora32_cfg_t *lora) {
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ESP_LOGD(TAG, "MODE_STANDBY");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STANDBY);
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}
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void lora32_sleep(lora32_cfg_t *lora) {
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ESP_LOGV(TAG, "MODE_SLEEP");
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ESP_LOGD(TAG, "MODE_SLEEP");
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
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}
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void lora32_enable_fhss(lora32_cfg_t *lora, uint8_t period) {
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lora->enableFHSS = true;
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lora32_write_reg(lora, REG_HOP_PERIOD, period);
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}
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void lora32_disable_fhss(lora32_cfg_t *lora) {
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lora->enableFHSS = false;
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lora32_write_reg(lora, REG_HOP_PERIOD, 0);
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}
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void lora32_enable_tx(lora32_cfg_t *lora) {
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lora32_standby(lora);
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lora32_idle(lora);
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if(lora->implicitHeader)
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lora23_set_implicit_header(lora);
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@ -133,8 +145,6 @@ void lora32_enable_tx(lora32_cfg_t *lora) {
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}
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void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
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ESP_ERROR_CHECK(spi_device_acquire_bus(lora->spi, portMAX_DELAY));
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lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_TXDONE);
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lora32_enable_tx(lora);
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@ -146,17 +156,15 @@ void lora32_send(lora32_cfg_t *lora, uint8_t *data, uint8_t len) {
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lora32_write_reg(lora, REG_PAYLOAD_LENGTH, len);
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lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
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spi_device_release_bus(lora->spi);
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}
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void lora32_set_frequency(lora32_cfg_t *lora, long frequency) {
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ESP_LOGD(TAG, "lora32_set_frequency: %lu", frequency);
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ESP_LOGI(TAG, "lora32_set_frequency: %lu", frequency);
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uint64_t frf = ((uint64_t)frequency << 19) / 32000000;
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ESP_LOGD(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
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ESP_LOGD(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
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ESP_LOGD(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
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ESP_LOGI(TAG, "REG_FRF_MSB: 0x%2X", (uint8_t)(frf >> 16));
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ESP_LOGI(TAG, "REG_FRF_MID: 0x%2X", (uint8_t)(frf >> 8));
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ESP_LOGI(TAG, "REG_FRF_LSB: 0x%2X", (uint8_t)(frf >> 0));
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lora32_write_reg(lora, REG_FRF_MSB, (uint8_t)(frf >> 16));
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lora32_write_reg(lora, REG_FRF_MID, (uint8_t)(frf >> 8));
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@ -194,7 +202,7 @@ void lora32_set_tx_power(lora32_cfg_t *lora, uint8_t level, uint8_t output) {
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lora32_write_reg(lora, REG_PA_CONFIG, PA_BOOST | (level - 2));
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}
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ESP_LOGD(TAG, "set_tx_power(%d, %d)", level, output);
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ESP_LOGI(TAG, "set_tx_power(%d, %d)", level, output);
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ESP_LOGD(TAG, "REG_PA_CONFIG: 0x%2X", lora32_read_reg(lora, REG_PA_CONFIG));
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}
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@ -231,7 +239,7 @@ void lora32_dump_regs(lora32_cfg_t *lora) {
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void lora32_toggle_reset(lora32_cfg_t *config) {
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// toggle reset (L/H)
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ESP_LOGD(TAG, "Toggling reset pin %d", config->reset);
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ESP_LOGI(TAG, "Toggling reset pin %d", config->reset);
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gpio_set_level(config->reset, 0);
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vTaskDelay(100 / portTICK_PERIOD_MS); // requires 100us
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@ -240,7 +248,7 @@ void lora32_toggle_reset(lora32_cfg_t *config) {
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vTaskDelay(100 / portTICK_PERIOD_MS); // 5ms before available
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}
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uint8_t lora32_get_spreadfactor(lora32_cfg_t *lora) {
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uint8_t lora32_get_spreadingfactor(lora32_cfg_t *lora) {
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return (lora32_read_reg(lora, REG_MODEM_CONFIG_2) >> 4);
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}
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@ -257,23 +265,9 @@ void lora32_set_spreadfactor(lora32_cfg_t *lora, uint8_t factor) {
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lora32_write_reg(lora, REG_DETECTION_THRESHOLD, DETECT_THRES_OTHER);
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}
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ESP_LOGV(TAG, "lora32_set_spreadfactor: %d", factor);
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ESP_LOGI(TAG, "lora32_set_spreadfactor: %d", factor);
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lora32_write_reg(lora, REG_MODEM_CONFIG_2, (lora32_read_reg(lora, REG_MODEM_CONFIG_2) & 0x0F) | ((factor << 4) & 0xF0));
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lora->spreadingFactor = factor;
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}
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void lora32_enable_single_rx(lora32_cfg_t *lora) {
|
||||
ESP_LOGD(TAG, "MODE_RX_SINGLE");
|
||||
|
||||
if(lora->receive != NULL) {
|
||||
lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
|
||||
}
|
||||
|
||||
lora32_standby(lora);
|
||||
|
||||
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
|
||||
}
|
||||
|
||||
void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
|
||||
|
|
@ -283,8 +277,6 @@ void lora32_enable_continuous_rx(lora32_cfg_t *lora) {
|
|||
lora32_write_reg(lora, REG_DIO_MAPPING_1, DIO0_MODE_RXDONE);
|
||||
}
|
||||
|
||||
lora32_standby(lora);
|
||||
|
||||
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
|
||||
}
|
||||
|
||||
|
|
@ -300,44 +292,34 @@ void lora32_enable_cad(lora32_cfg_t *lora) {
|
|||
lora32_write_reg(lora, REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_CAD_DETECT);
|
||||
}
|
||||
|
||||
int16_t lora32_get_rssi(lora32_cfg_t *lora) {
|
||||
// TODO support LF output constant of -164
|
||||
return -157 + lora32_read_reg(lora, REG_RSSI_VALUE);
|
||||
}
|
||||
|
||||
int16_t lora32_get_packet_rssi(lora32_cfg_t *lora) {
|
||||
// TODO support LF output constant of -164
|
||||
return -157 + lora32_read_reg(lora, REG_PKT_RSSI_VALUE);
|
||||
}
|
||||
|
||||
long lora32_get_bandwidth(lora32_cfg_t *lora) {
|
||||
uint8_t bw = (lora32_read_reg(lora, REG_MODEM_CONFIG_1) >> 4);
|
||||
ESP_LOGV(TAG, "lora32_get_bandwidth: %d", bw);
|
||||
ESP_LOGI(TAG, "lora32_get_bandwidth: %d", bw);
|
||||
|
||||
if(bw > 9) return -1;
|
||||
|
||||
ESP_LOGD(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]);
|
||||
ESP_LOGI(TAG, "lora32_get_bandwidth: %ld", bandwidths[bw]);
|
||||
|
||||
return bandwidths[bw];
|
||||
}
|
||||
|
||||
void lora32_set_ldo_flag(lora32_cfg_t *lora) {
|
||||
long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadfactor(lora)));
|
||||
long symbolDuration = 1000 / (lora32_get_bandwidth(lora) / (1L << lora32_get_spreadingfactor(lora)));
|
||||
|
||||
ESP_LOGD(TAG, "symbolDuration: %ld", symbolDuration);
|
||||
ESP_LOGI(TAG, "symbolDuration: %ld", symbolDuration);
|
||||
|
||||
bool ldoOn = symbolDuration > 16;
|
||||
ESP_LOGD(TAG, "ldoOn: %d", ldoOn);
|
||||
ESP_LOGI(TAG, "ldoOn: %d", ldoOn);
|
||||
|
||||
uint8_t modem_config_3 = lora32_read_reg(lora, REG_MODEM_CONFIG_3);
|
||||
ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3);
|
||||
ESP_LOGI(TAG, "modem_config_3: %d", modem_config_3);
|
||||
modem_config_3 |= ldoOn << 3;
|
||||
ESP_LOGD(TAG, "modem_config_3: %d", modem_config_3);
|
||||
ESP_LOGI(TAG, "modem_config_3: %d", modem_config_3);
|
||||
lora32_write_reg(lora, REG_MODEM_CONFIG_3, modem_config_3);
|
||||
}
|
||||
|
||||
void lora32_set_bandwidth(lora32_cfg_t *lora, uint8_t bw) {
|
||||
ESP_LOGD(TAG, "lora32_set_bandwidth: %d", bw);
|
||||
ESP_LOGI(TAG, "lora32_set_bandwidth: %d", bw);
|
||||
|
||||
uint8_t modem_config_1 = lora32_read_reg(lora, REG_MODEM_CONFIG_1);
|
||||
lora32_write_reg(lora, REG_MODEM_CONFIG_1, (modem_config_1 & 0x0F) | (bw << 4));
|
||||
|
|
@ -351,7 +333,7 @@ void lora32_set_coding_rate(lora32_cfg_t *lora, uint8_t cr) {
|
|||
|
||||
cr = cr - 4;
|
||||
|
||||
ESP_LOGD(TAG, "lora32_set_coding_rate: %d", cr + 4);
|
||||
ESP_LOGI(TAG, "lora32_set_coding_rate: %d", cr + 4);
|
||||
|
||||
lora32_write_reg(lora, REG_MODEM_CONFIG_1, (lora32_read_reg(lora, REG_MODEM_CONFIG_1) & 0xF1) | (cr << 1));
|
||||
}
|
||||
|
|
@ -365,7 +347,7 @@ void lora32_set_lna(lora32_cfg_t *lora, uint8_t gain) {
|
|||
uint8_t lna = lora32_read_reg(lora, REG_LNA);
|
||||
|
||||
lora32_write_reg(lora, REG_LNA, lna | gain);
|
||||
ESP_LOGD(TAG, "set lna: 0x%2X", lna | gain);
|
||||
ESP_LOGI(TAG, "set lna: 0x%2X", lna | gain);
|
||||
}
|
||||
|
||||
static void lora32_handle_receive(lora32_cfg_t *lora) {
|
||||
|
|
@ -378,40 +360,35 @@ static void lora32_handle_receive(lora32_cfg_t *lora) {
|
|||
|
||||
lora32_write_reg(lora, REG_FIFO_ADDR_PTR, fifo_addr);
|
||||
|
||||
lora->receive(lora, len);
|
||||
lora->receive(len);
|
||||
}
|
||||
|
||||
static void IRAM_ATTR lora32_dio_task(void *arg) {
|
||||
// allocate lora32_cfg_t to receive config from Queu
|
||||
lora32_cfg_t *lora = malloc(sizeof(lora32_cfg_t));
|
||||
ESP_LOGD(TAG, "starting DIO handler task");
|
||||
static void IRAM_ATTR lora32_dio0_task(void *arg) {
|
||||
lora32_cfg_t *lora = (lora32_cfg_t*)arg;
|
||||
ESP_LOGD(TAG, "starting DIO0 handler task");
|
||||
|
||||
while(1) {
|
||||
// wait for event over Queue
|
||||
if(xQueueReceive(dio_event_queue, (void*)&lora, portMAX_DELAY) != pdPASS) continue;
|
||||
EventBits_t evbits = xEventGroupWaitBits(lora->handle.events, EV_DIO0, pdTRUE, pdFALSE, 5000 / portTICK_PERIOD_MS);
|
||||
|
||||
// need a better way to log which event and from which config
|
||||
//ESP_LOGI(TAG, "handling DIO0 on GPIO%d", lora->dio0);
|
||||
// timed out, loop and continue to wait
|
||||
if(evbits == 0) continue;
|
||||
|
||||
spi_device_acquire_bus(lora->spi, portMAX_DELAY);
|
||||
ESP_LOGD(TAG, "handling DIO0");
|
||||
|
||||
// read IRQ flags
|
||||
uint8_t irqs = lora32_read_reg(lora, REG_IRQ_FLAGS);
|
||||
ESP_LOGD(TAG, "reading irqs: %02X", irqs);
|
||||
|
||||
// clear IRQ flags by writing mask back
|
||||
// clear IRQ flags
|
||||
ESP_LOGD(TAG, "clearing irqs");
|
||||
lora32_write_reg(lora, REG_IRQ_FLAGS, irqs);
|
||||
|
||||
spi_device_release_bus(lora->spi);
|
||||
|
||||
// TODO handle header validation
|
||||
if((irqs & IRQ_RX_DONE) == IRQ_RX_DONE) {
|
||||
lora32_handle_receive(lora);
|
||||
}
|
||||
|
||||
if((irqs & IRQ_TX_DONE) == IRQ_TX_DONE) {
|
||||
if(lora->tx_done != NULL) lora->tx_done(lora);
|
||||
if(lora->tx_done != NULL) lora->tx_done();
|
||||
}
|
||||
|
||||
bool cad_detected = false;
|
||||
|
|
@ -421,28 +398,13 @@ static void IRAM_ATTR lora32_dio_task(void *arg) {
|
|||
cad_detected = true;
|
||||
|
||||
// no need for arg, cad_detected callback is always presummed true
|
||||
if(lora->cad_detected != NULL) lora->cad_detected(lora);
|
||||
if(lora->cad_detected != NULL) lora->cad_detected();
|
||||
}
|
||||
|
||||
if((irqs & IRQ_CAD_DONE) == IRQ_CAD_DONE) {
|
||||
// cad_done gets true/false from above, when activity is detected
|
||||
// these *should* fire at the same time, defaults to false
|
||||
if(lora->cad_done != NULL) lora->cad_done(lora, cad_detected);
|
||||
}
|
||||
|
||||
if((irqs & IRQ_FHSS_CHANGE) == IRQ_FHSS_CHANGE) {
|
||||
ESP_LOGD(TAG, "switching channel %d: %d", lora->channel, lora->channels[lora->channel]);
|
||||
|
||||
if(lora->channel == 0 && lora->channels[lora->channel] == 0) continue;
|
||||
|
||||
if(lora->channels[lora->channel] == 0) {
|
||||
ESP_LOGD(TAG, "reseting to channel 0");
|
||||
lora->channel = 0;
|
||||
}
|
||||
|
||||
lora32_set_frequency(lora, lora->frequency + (lora->channels[lora->channel] * bandwidths[lora->bandwidth]));
|
||||
|
||||
lora->channel++;
|
||||
if(lora->cad_done != NULL) lora->cad_done(cad_detected);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -451,43 +413,20 @@ void lora32_read_data(lora32_cfg_t *lora, uint8_t *data) {
|
|||
uint8_t i = 0;
|
||||
uint8_t len = lora32_read_reg(lora, (lora->implicitHeader ? REG_PAYLOAD_LENGTH : REG_RX_NB_BYTES));
|
||||
|
||||
ESP_LOGD(TAG, "Reading %d bytes", len);
|
||||
ESP_LOGI(TAG, "Reading %d bytes", len);
|
||||
|
||||
for(i = 0; i < len; i++) {
|
||||
data[i] = lora32_read_reg(lora, REG_FIFO);
|
||||
}
|
||||
}
|
||||
|
||||
static void IRAM_ATTR lora32_on_dio(void *arg) {
|
||||
xQueueSendFromISR(dio_event_queue, (void*)&arg, pdFALSE);
|
||||
}
|
||||
static void IRAM_ATTR lora32_on_dio0(void *arg) {
|
||||
BaseType_t woken = pdFALSE;
|
||||
|
||||
uint8_t lora32_spi_init(lora32_cfg_t *lora) {
|
||||
ESP_LOGD(TAG, "Initializing SPI bus");
|
||||
|
||||
esp_err_t err = ESP_OK;
|
||||
|
||||
spi_bus_config_t buscfg = {
|
||||
.miso_io_num = lora->cipo,
|
||||
.mosi_io_num = lora->copi,
|
||||
.sclk_io_num = lora->clk,
|
||||
.quadwp_io_num = -1,
|
||||
.quadhd_io_num = -1
|
||||
};
|
||||
|
||||
if(spi_bus_get_attr(lora->spi_host) == NULL) {
|
||||
// 2 should be SPI_DMA_CH_AUTO ??? but it doesn't seem to be defined
|
||||
err = spi_bus_initialize(lora->spi_host, &buscfg, 2);
|
||||
}
|
||||
|
||||
return err;
|
||||
xEventGroupSetBitsFromISR(((lora32_cfg_t*)arg)->handle.events, EV_DIO0, &woken);
|
||||
}
|
||||
|
||||
uint8_t lora32_init(lora32_cfg_t *lora) {
|
||||
if(spi_semaphore == NULL) {
|
||||
spi_semaphore = xSemaphoreCreateMutex();
|
||||
}
|
||||
|
||||
gpio_config_t io_conf;
|
||||
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
|
||||
io_conf.mode = GPIO_MODE_OUTPUT;
|
||||
|
|
@ -499,12 +438,24 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
|
|||
|
||||
lora32_toggle_reset(lora);
|
||||
// set NSS high
|
||||
ESP_LOGD(TAG, "Bringing NSS high: %d", lora->nss);
|
||||
ESP_LOGI(TAG, "Bringing NSS high: %d", lora->nss);
|
||||
gpio_set_level(lora->nss, 1);
|
||||
|
||||
vTaskDelay(10 / portTICK_PERIOD_MS);
|
||||
|
||||
// SPI device setup
|
||||
// init spi
|
||||
ESP_LOGI(TAG, "Initializing SPI bus");
|
||||
// TODO fix this awkward log along with pin assignments in general
|
||||
ESP_LOGI(TAG, "\n MISO: %d\nMOSI: %d\nCLK: %d\nNSS: %d", PIN_NUM_MISO, PIN_NUM_MOSI, PIN_NUM_CLK, lora->nss);
|
||||
|
||||
spi_bus_config_t buscfg = {
|
||||
.miso_io_num = PIN_NUM_MISO,
|
||||
.mosi_io_num = PIN_NUM_MOSI,
|
||||
.sclk_io_num = PIN_NUM_CLK,
|
||||
.quadwp_io_num = -1,
|
||||
.quadhd_io_num = -1
|
||||
};
|
||||
|
||||
spi_device_interface_config_t devcfg = {
|
||||
.clock_speed_hz = 8E6,
|
||||
.flags = 0,
|
||||
|
|
@ -513,26 +464,19 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
|
|||
.queue_size = 7,
|
||||
};
|
||||
|
||||
ESP_ERROR_CHECK(spi_bus_add_device(lora->spi_host, &devcfg, &lora->spi));
|
||||
ESP_ERROR_CHECK(spi_bus_initialize(HSPI_HOST, &buscfg, 0));
|
||||
ESP_ERROR_CHECK(spi_bus_add_device(HSPI_HOST, &devcfg, &lora->spi));
|
||||
|
||||
// initialize event groups
|
||||
lora->handle.events = xEventGroupCreate();
|
||||
|
||||
uint8_t version = lora32_read_reg(lora, REG_VERSION);
|
||||
ESP_LOGD(TAG, "lora32_get_id() == 0x%2X", version);
|
||||
|
||||
lora->version = version;
|
||||
|
||||
// if ID does not match, something is likely wrong on the SPI bus
|
||||
if(version != 0x12) {
|
||||
ESP_LOGE(TAG, "REG_VERSION returned incorrectly. Expected 0x12 got 0x%02X", version);
|
||||
|
||||
return ERR_LOR_VERSION_MISMATCH;
|
||||
}
|
||||
assert(version == 0x12);
|
||||
|
||||
// TODO: confirm this is happening. Before/after power measurements?
|
||||
lora32_sleep(lora);
|
||||
ESP_LOGV(TAG, "lora32_sleep");
|
||||
ESP_LOGI(TAG, "lora32_sleep");
|
||||
|
||||
// TODO: VERIFY
|
||||
lora32_set_frequency(lora, lora->frequency);
|
||||
|
|
@ -542,7 +486,7 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
|
|||
|
||||
lora32_write_reg(lora, REG_FIFO_TX_BASE_ADDR, 0x00);
|
||||
lora32_write_reg(lora, REG_FIFO_RX_BASE_ADDR, 0x00);
|
||||
ESP_LOGV(TAG, "clear rx/tx fifos");
|
||||
ESP_LOGI(TAG, "clear rx/tx fifos");
|
||||
|
||||
lora32_set_lna(lora, 0x03);
|
||||
|
||||
|
|
@ -551,61 +495,30 @@ uint8_t lora32_init(lora32_cfg_t *lora) {
|
|||
|
||||
// TODO make based on config
|
||||
lora32_set_tx_power(lora, 17, PA_OUTPUT_PA_BOOST_PIN);
|
||||
ESP_LOGV(TAG, "lora32_set_tx_power");
|
||||
ESP_LOGI(TAG, "lora32_set_tx_power");
|
||||
|
||||
lora32_standby(lora);
|
||||
ESP_LOGV(TAG, "lora32_standby");
|
||||
|
||||
if(lora->implicitHeader)
|
||||
lora23_set_implicit_header(lora);
|
||||
else
|
||||
lora23_set_explicit_header(lora);
|
||||
lora32_idle(lora);
|
||||
ESP_LOGI(TAG, "lora32_idle");
|
||||
|
||||
// TODO setup shouldn't be based on just receive callback
|
||||
if(lora->receive != NULL) {
|
||||
ESP_LOGV(TAG, "Setting GPIO Interrupt");
|
||||
|
||||
// TODO check at least one DIOx pin is not NULL
|
||||
|
||||
uint64_t pin_bit_mask = 0;
|
||||
if(lora->dio0 > -1)
|
||||
pin_bit_mask |= (1 << lora->dio0);
|
||||
if(lora->dio1 > -1)
|
||||
pin_bit_mask |= (1 << lora->dio1);
|
||||
if(lora->dio2 > -1)
|
||||
pin_bit_mask |= (1 << lora->dio2);
|
||||
ESP_LOGI(TAG, "Setting callback handler");
|
||||
|
||||
io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
|
||||
io_conf.pin_bit_mask = pin_bit_mask;
|
||||
io_conf.pin_bit_mask = (1ULL << CONFIG_LORA32_DIO0_PIN);
|
||||
io_conf.mode = GPIO_MODE_INPUT;
|
||||
io_conf.pull_down_en = 1;
|
||||
io_conf.pull_down_en = 0;
|
||||
io_conf.pull_up_en = 0;
|
||||
gpio_config(&io_conf);
|
||||
|
||||
// the DIO interrupt handling for every device is done from one task
|
||||
if(dio_task_handle == NULL) {
|
||||
ESP_LOGV(TAG, "Setting callback handler and ISR service");
|
||||
|
||||
// enable global ISR service
|
||||
gpio_set_intr_type(CONFIG_LORA32_DIO0_PIN, GPIO_INTR_POSEDGE);
|
||||
gpio_install_isr_service(0);
|
||||
|
||||
dio_event_queue = xQueueCreate(10, sizeof(lora32_cfg_t *));
|
||||
gpio_isr_handler_add(CONFIG_LORA32_DIO0_PIN, lora32_on_dio0, (void*)lora);
|
||||
|
||||
// this should probably be high priority
|
||||
xTaskCreate(&lora32_dio_task, "lora32_dio_task", 4096, NULL, 6, &dio_task_handle);
|
||||
xTaskCreate(&lora32_dio0_task, "lora32_dio0_task", 14048, (void*)lora, 6, NULL);
|
||||
}
|
||||
|
||||
// add ISR handler to the global service started (once) above
|
||||
ESP_LOGV(TAG, "Installing ISR handler for GPIO%d", lora->dio0);
|
||||
if(lora->dio0 > -1)
|
||||
gpio_isr_handler_add(lora->dio0, lora32_on_dio, (void*)lora);
|
||||
|
||||
if(lora->dio1 > -1)
|
||||
gpio_isr_handler_add(lora->dio1, lora32_on_dio, (void*)lora);
|
||||
|
||||
if(lora->dio2 > -1)
|
||||
gpio_isr_handler_add(lora->dio2, lora32_on_dio, (void*)lora);
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
return 1;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue