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changed to SOICbite style programming header

This commit is contained in:
Morgan 'ARR\!' Allen 2019-06-27 21:49:55 -07:00
parent 62c1f13279
commit 93647862a5
5 changed files with 1540 additions and 1333 deletions
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3
.gitmodules vendored Normal file
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@ -0,0 +1,3 @@
[submodule "SOICbite"]
path = SOICbite
url = https://github.com/SimonMerrett/SOICbite.git

1
SOICbite Submodule

@ -0,0 +1 @@
Subproject commit e031eff57bbc582c15580f2224f606f677a9f16e

2543
ricmohte.kicad_pcb
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File diff suppressed because it is too large Load Diff

248
ricmohte.pro
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@ -1,30 +1,10 @@
update=05/04/2019 20:44:53
update=Thu 27 Jun 2019 09:27:25 PM PDT
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
CopperEdgeClearance=0.000000000000
[cvpcb]
version=1
NetIExt=net
@ -32,3 +12,229 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.1524
TrackWidth3=0.2
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

78
ricmohte.sch
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@ -26,17 +26,6 @@ F 3 "https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32_
1 0 0 -1
$EndComp
$Comp
L Connector:Conn_01x06_Female J1
U 1 1 5CE4C072
P 5200 1900
F 0 "J1" H 5092 1375 50 0000 C CNN
F 1 "Conn_01x06_Female" H 5092 1466 50 0000 C CNN
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x06_P2.54mm_Horizontal" H 5200 1900 50 0001 C CNN
F 3 "~" H 5200 1900 50 0001 C CNN
1 5200 1900
-1 0 0 1
$EndComp
$Comp
L Connector:USB_B_Micro J2
U 1 1 5CE4EB7C
P 7550 1800
@ -208,24 +197,9 @@ F 3 "" H 5600 2100 50 0001 C CNN
1 5600 2100
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0108
U 1 1 5CEAA5BD
P 5600 2000
F 0 "#PWR0108" H 5600 1750 50 0001 C CNN
F 1 "GND" V 5605 1872 50 0000 R CNN
F 2 "" H 5600 2000 50 0001 C CNN
F 3 "" H 5600 2000 50 0001 C CNN
1 5600 2000
0 -1 -1 0
$EndComp
Text GLabel 5600 1900 2 50 Input ~ 0
IO0
Text GLabel 5600 1800 2 50 Input ~ 0
EN
Text GLabel 5600 1600 2 50 Input ~ 0
TX
Text GLabel 5600 1700 2 50 Input ~ 0
RX
Wire Wire Line
5400 1600 5600 1600
@ -567,4 +541,56 @@ F 3 "~" H 10650 3300 50 0001 C CNN
1 10650 3300
-1 0 0 -1
$EndComp
$Comp
L Connector:Conn_01x08_Female J1
U 1 1 5D1985B1
P 5200 1800
F 0 "J1" H 5200 2300 50 0000 C CNN
F 1 "Conn_01x08_Female" H 4850 2200 50 0000 C CNN
F 2 "SOICbite:SOIC_clipProgSmall" H 5200 1800 50 0001 C CNN
F 3 "~" H 5200 1800 50 0001 C CNN
1 5200 1800
-1 0 0 1
$EndComp
$Comp
L power:+3V3 #PWR0117
U 1 1 5D1AFDFA
P 5600 1700
F 0 "#PWR0117" H 5600 1550 50 0001 C CNN
F 1 "+3V3" V 5615 1828 50 0000 L CNN
F 2 "" H 5600 1700 50 0001 C CNN
F 3 "" H 5600 1700 50 0001 C CNN
1 5600 1700
0 1 -1 0
$EndComp
Wire Wire Line
5400 1400 5600 1400
Wire Wire Line
5600 1500 5400 1500
Text GLabel 5600 2000 2 50 Input ~ 0
EN
$Comp
L power:GND #PWR0108
U 1 1 5CEAA5BD
P 5600 1800
F 0 "#PWR0108" H 5600 1550 50 0001 C CNN
F 1 "GND" V 5605 1672 50 0000 R CNN
F 2 "" H 5600 1800 50 0001 C CNN
F 3 "" H 5600 1800 50 0001 C CNN
1 5600 1800
0 -1 -1 0
$EndComp
Text GLabel 5600 1500 2 50 Input ~ 0
TX
$Comp
L power:GND #PWR0118
U 1 1 5D1AFE04
P 5600 1400
F 0 "#PWR0118" H 5600 1150 50 0001 C CNN
F 1 "GND" V 5605 1272 50 0000 R CNN
F 2 "" H 5600 1400 50 0001 C CNN
F 3 "" H 5600 1400 50 0001 C CNN
1 5600 1400
0 -1 1 0
$EndComp
$EndSCHEMATC