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merge into: morgan:development
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morgan:development
morgan:soft-test
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pull from: morgan:soft-test
Branches Tags
morgan:development
morgan:soft-test

2 commits
developmen ... soft-test

Author SHA1 Message Date
Morgan 'ARR\!' Allen
61854e47f9 some change 2019-08-19 12:22:16 -07:00
Morgan 'ARR\!' Allen
9246f493ef circuit milled for test 2019-08-18 21:53:52 -07:00
2 changed files with 898 additions and 2515 deletions
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2022
ricmohte.kicad_pcb Normal file → Executable file
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23
ricmohte.pro Normal file → Executable file
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@ -1,4 +1,4 @@
update=Thu 15 Aug 2019 07:27:23 PM PDT update=8/18/2019 5:07:19 PM
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
@ -12,6 +12,16 @@ NetIExt=net
version=1 version=1
LibDir= LibDir=
[eeschema/libraries] [eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=59
ERC_TestSimilarLabels=1
[pcbnew] [pcbnew]
version=1 version=1
PageLayoutDescrFile= PageLayoutDescrFile=
@ -31,6 +41,7 @@ MinHoleToHole=0.25
TrackWidth1=0.1524 TrackWidth1=0.1524
TrackWidth2=0.1524 TrackWidth2=0.1524
TrackWidth3=0.2 TrackWidth3=0.2
TrackWidth4=0.5
ViaDiameter1=0.8 ViaDiameter1=0.8
ViaDrill1=0.4 ViaDrill1=0.4
dPairWidth1=0.2 dPairWidth1=0.2
@ -238,13 +249,3 @@ uViaDrill=0.1
dPairWidth=0.2 dPairWidth=0.2
dPairGap=0.25 dPairGap=0.25
dPairViaGap=0.25 dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=59
ERC_TestSimilarLabels=1