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morgan:soft-test
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morgan:soft-test

2 commits
developmen ... soft-test

Author SHA1 Message Date
Morgan 'ARR\!' Allen
61854e47f9 some change 2019-08-19 12:22:16 -07:00
Morgan 'ARR\!' Allen
9246f493ef circuit milled for test 2019-08-18 21:53:52 -07:00
2 changed files with 898 additions and 2515 deletions
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2912
ricmohte.kicad_pcb Normal file → Executable file
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File diff suppressed because it is too large Load diff

501
ricmohte.pro Normal file → Executable file
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@ -1,250 +1,251 @@
update=Thu 15 Aug 2019 07:27:23 PM PDT update=8/18/2019 5:07:19 PM
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
version=1 version=1
RootSch= RootSch=
BoardNm= BoardNm=
[cvpcb] [cvpcb]
version=1 version=1
NetIExt=net NetIExt=net
[eeschema] [eeschema]
version=1 version=1
LibDir= LibDir=
[eeschema/libraries] [eeschema/libraries]
[pcbnew] [schematic_editor]
version=1 version=1
PageLayoutDescrFile= PageLayoutDescrFile=
LastNetListRead= PlotDirectoryName=
CopperLayerCount=2 SubpartIdSeparator=0
BoardThickness=1.6 SubpartFirstId=65
AllowMicroVias=0 NetFmtName=
AllowBlindVias=0 SpiceAjustPassiveValues=0
RequireCourtyardDefinitions=0 LabSize=59
ProhibitOverlappingCourtyards=1 ERC_TestSimilarLabels=1
MinTrackWidth=0.1524 [pcbnew]
MinViaDiameter=0.4 version=1
MinViaDrill=0.3 PageLayoutDescrFile=
MinMicroViaDiameter=0.2 LastNetListRead=
MinMicroViaDrill=0.09999999999999999 CopperLayerCount=2
MinHoleToHole=0.25 BoardThickness=1.6
TrackWidth1=0.1524 AllowMicroVias=0
TrackWidth2=0.1524 AllowBlindVias=0
TrackWidth3=0.2 RequireCourtyardDefinitions=0
ViaDiameter1=0.8 ProhibitOverlappingCourtyards=1
ViaDrill1=0.4 MinTrackWidth=0.1524
dPairWidth1=0.2 MinViaDiameter=0.4
dPairGap1=0.25 MinViaDrill=0.3
dPairViaGap1=0.25 MinMicroViaDiameter=0.2
SilkLineWidth=0.12 MinMicroViaDrill=0.09999999999999999
SilkTextSizeV=1 MinHoleToHole=0.25
SilkTextSizeH=1 TrackWidth1=0.1524
SilkTextSizeThickness=0.15 TrackWidth2=0.1524
SilkTextItalic=0 TrackWidth3=0.2
SilkTextUpright=1 TrackWidth4=0.5
CopperLineWidth=0.2 ViaDiameter1=0.8
CopperTextSizeV=1.5 ViaDrill1=0.4
CopperTextSizeH=1.5 dPairWidth1=0.2
CopperTextThickness=0.3 dPairGap1=0.25
CopperTextItalic=0 dPairViaGap1=0.25
CopperTextUpright=1 SilkLineWidth=0.12
EdgeCutLineWidth=0.05 SilkTextSizeV=1
CourtyardLineWidth=0.05 SilkTextSizeH=1
OthersLineWidth=0.15 SilkTextSizeThickness=0.15
OthersTextSizeV=1 SilkTextItalic=0
OthersTextSizeH=1 SilkTextUpright=1
OthersTextSizeThickness=0.15 CopperLineWidth=0.2
OthersTextItalic=0 CopperTextSizeV=1.5
OthersTextUpright=1 CopperTextSizeH=1.5
SolderMaskClearance=0.051 CopperTextThickness=0.3
SolderMaskMinWidth=0.25 CopperTextItalic=0
SolderPasteClearance=0 CopperTextUpright=1
SolderPasteRatio=-0 EdgeCutLineWidth=0.05
[pcbnew/Layer.F.Cu] CourtyardLineWidth=0.05
Name=F.Cu OthersLineWidth=0.15
Type=0 OthersTextSizeV=1
Enabled=1 OthersTextSizeH=1
[pcbnew/Layer.In1.Cu] OthersTextSizeThickness=0.15
Name=In1.Cu OthersTextItalic=0
Type=0 OthersTextUpright=1
Enabled=0 SolderMaskClearance=0.051
[pcbnew/Layer.In2.Cu] SolderMaskMinWidth=0.25
Name=In2.Cu SolderPasteClearance=0
Type=0 SolderPasteRatio=-0
Enabled=0 [pcbnew/Layer.F.Cu]
[pcbnew/Layer.In3.Cu] Name=F.Cu
Name=In3.Cu Type=0
Type=0 Enabled=1
Enabled=0 [pcbnew/Layer.In1.Cu]
[pcbnew/Layer.In4.Cu] Name=In1.Cu
Name=In4.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In2.Cu]
[pcbnew/Layer.In5.Cu] Name=In2.Cu
Name=In5.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In3.Cu]
[pcbnew/Layer.In6.Cu] Name=In3.Cu
Name=In6.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In4.Cu]
[pcbnew/Layer.In7.Cu] Name=In4.Cu
Name=In7.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In5.Cu]
[pcbnew/Layer.In8.Cu] Name=In5.Cu
Name=In8.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In6.Cu]
[pcbnew/Layer.In9.Cu] Name=In6.Cu
Name=In9.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In7.Cu]
[pcbnew/Layer.In10.Cu] Name=In7.Cu
Name=In10.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In8.Cu]
[pcbnew/Layer.In11.Cu] Name=In8.Cu
Name=In11.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In9.Cu]
[pcbnew/Layer.In12.Cu] Name=In9.Cu
Name=In12.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In10.Cu]
[pcbnew/Layer.In13.Cu] Name=In10.Cu
Name=In13.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In11.Cu]
[pcbnew/Layer.In14.Cu] Name=In11.Cu
Name=In14.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In12.Cu]
[pcbnew/Layer.In15.Cu] Name=In12.Cu
Name=In15.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In13.Cu]
[pcbnew/Layer.In16.Cu] Name=In13.Cu
Name=In16.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In14.Cu]
[pcbnew/Layer.In17.Cu] Name=In14.Cu
Name=In17.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In15.Cu]
[pcbnew/Layer.In18.Cu] Name=In15.Cu
Name=In18.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In16.Cu]
[pcbnew/Layer.In19.Cu] Name=In16.Cu
Name=In19.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In17.Cu]
[pcbnew/Layer.In20.Cu] Name=In17.Cu
Name=In20.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In18.Cu]
[pcbnew/Layer.In21.Cu] Name=In18.Cu
Name=In21.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In19.Cu]
[pcbnew/Layer.In22.Cu] Name=In19.Cu
Name=In22.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In20.Cu]
[pcbnew/Layer.In23.Cu] Name=In20.Cu
Name=In23.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In21.Cu]
[pcbnew/Layer.In24.Cu] Name=In21.Cu
Name=In24.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In22.Cu]
[pcbnew/Layer.In25.Cu] Name=In22.Cu
Name=In25.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In23.Cu]
[pcbnew/Layer.In26.Cu] Name=In23.Cu
Name=In26.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In24.Cu]
[pcbnew/Layer.In27.Cu] Name=In24.Cu
Name=In27.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In25.Cu]
[pcbnew/Layer.In28.Cu] Name=In25.Cu
Name=In28.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In26.Cu]
[pcbnew/Layer.In29.Cu] Name=In26.Cu
Name=In29.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In27.Cu]
[pcbnew/Layer.In30.Cu] Name=In27.Cu
Name=In30.Cu Type=0
Type=0 Enabled=0
Enabled=0 [pcbnew/Layer.In28.Cu]
[pcbnew/Layer.B.Cu] Name=In28.Cu
Name=B.Cu Type=0
Type=0 Enabled=0
Enabled=1 [pcbnew/Layer.In29.Cu]
[pcbnew/Layer.B.Adhes] Name=In29.Cu
Enabled=1 Type=0
[pcbnew/Layer.F.Adhes] Enabled=0
Enabled=1 [pcbnew/Layer.In30.Cu]
[pcbnew/Layer.B.Paste] Name=In30.Cu
Enabled=1 Type=0
[pcbnew/Layer.F.Paste] Enabled=0
Enabled=1 [pcbnew/Layer.B.Cu]
[pcbnew/Layer.B.SilkS] Name=B.Cu
Enabled=1 Type=0
[pcbnew/Layer.F.SilkS] Enabled=1
Enabled=1 [pcbnew/Layer.B.Adhes]
[pcbnew/Layer.B.Mask] Enabled=1
Enabled=1 [pcbnew/Layer.F.Adhes]
[pcbnew/Layer.F.Mask] Enabled=1
Enabled=1 [pcbnew/Layer.B.Paste]
[pcbnew/Layer.Dwgs.User] Enabled=1
Enabled=1 [pcbnew/Layer.F.Paste]
[pcbnew/Layer.Cmts.User] Enabled=1
Enabled=1 [pcbnew/Layer.B.SilkS]
[pcbnew/Layer.Eco1.User] Enabled=1
Enabled=1 [pcbnew/Layer.F.SilkS]
[pcbnew/Layer.Eco2.User] Enabled=1
Enabled=1 [pcbnew/Layer.B.Mask]
[pcbnew/Layer.Edge.Cuts] Enabled=1
Enabled=1 [pcbnew/Layer.F.Mask]
[pcbnew/Layer.Margin] Enabled=1
Enabled=1 [pcbnew/Layer.Dwgs.User]
[pcbnew/Layer.B.CrtYd] Enabled=1
Enabled=1 [pcbnew/Layer.Cmts.User]
[pcbnew/Layer.F.CrtYd] Enabled=1
Enabled=1 [pcbnew/Layer.Eco1.User]
[pcbnew/Layer.B.Fab] Enabled=1
Enabled=1 [pcbnew/Layer.Eco2.User]
[pcbnew/Layer.F.Fab] Enabled=1
Enabled=1 [pcbnew/Layer.Edge.Cuts]
[pcbnew/Layer.Rescue] Enabled=1
Enabled=0 [pcbnew/Layer.Margin]
[pcbnew/Netclasses] Enabled=1
[pcbnew/Netclasses/Default] [pcbnew/Layer.B.CrtYd]
Name=Default Enabled=1
Clearance=0.1524 [pcbnew/Layer.F.CrtYd]
TrackWidth=0.1524 Enabled=1
ViaDiameter=0.8 [pcbnew/Layer.B.Fab]
ViaDrill=0.4 Enabled=1
uViaDiameter=0.3 [pcbnew/Layer.F.Fab]
uViaDrill=0.1 Enabled=1
dPairWidth=0.2 [pcbnew/Layer.Rescue]
dPairGap=0.25 Enabled=0
dPairViaGap=0.25 [pcbnew/Netclasses]
[schematic_editor] [pcbnew/Netclasses/Default]
version=1 Name=Default
PageLayoutDescrFile= Clearance=0.1524
PlotDirectoryName= TrackWidth=0.1524
SubpartIdSeparator=0 ViaDiameter=0.8
SubpartFirstId=65 ViaDrill=0.4
NetFmtName= uViaDiameter=0.3
SpiceAjustPassiveValues=0 uViaDrill=0.1
LabSize=59 dPairWidth=0.2
ERC_TestSimilarLabels=1 dPairGap=0.25
dPairViaGap=0.25