morgan · he/him
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  • Joined on 2021-09-21
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morgan pushed to development at morgan/esp32-lora 2021-12-09 00:28:35 -05:00
d7db736937 include name
e912b54cba Merge branch 'fhss' into fhss-merge (development)
d93f3399bc properly handle _cfg_t pointers for ISR handling scheme
c5dc9c961d add new dio handlers, consolidate DIO handlers to single function
a347f418c8 add FHSS IRQ handling
Compare 8 commits »
morgan commented on issue morgan/esp32-dual-lora#2 2021-12-08 01:15:13 -05:00
Add pull-down resisitors to RESET and NSS

Leaving RESET floating is defenitly causing issues. Unless the init code explicitly pulls LORA2_RESET LOW LoRa 1 is likely to fail init.

morgan opened issue morgan/esp32-lora#13 2021-12-07 21:14:10 -05:00
IntegerDivideByZero related to get_bandwidth returning incorrect value
morgan commented on issue morgan/esp32-lora#12 2021-12-07 20:10:25 -05:00
verify bandwidth register is set correctly. 
I (681) LoRa32: lora32_set_bandwidth: 8
I (691) LoRa32: lora32_get_bandwidth: 13
morgan opened issue morgan/esp32-lora#12 2021-12-07 13:10:29 -05:00
verify bandwidth register is set correctly.
morgan created branch fhss in morgan/esp32-lora 2021-12-02 13:03:20 -05:00
morgan pushed to fhss at morgan/esp32-lora 2021-12-02 13:03:20 -05:00
c5dc9c961d add new dio handlers, consolidate DIO handlers to single function
a347f418c8 add FHSS IRQ handling
6ad9cba796 add primary enable/disable functions for FHSS
b476a41c92 add more dio pins to lora_cfg, channels, (en/dis)able methods for FHSS
1396434448 add register for FHSS
Compare 5 commits »
morgan opened issue morgan/esp32-lora#11 2021-12-02 01:47:23 -05:00
Implement DIO mapping
morgan pushed to development at morgan/esp32-lora 2021-11-19 13:56:20 -05:00
c8beb458f6 set header mode during init based on lora32_cfg_t->implicitHeader state
7ec011f15a debug log setting header mode
db9b74ec76 renamed idle to standby to better reflect datasheet
14cd5df1e3 implement single RX, still needs timeout handling
8f07873624 reimplementing semephore and bus locking seems to have helped overall stability, particularly on first init
Compare 8 commits »
morgan opened issue morgan/esp32-lora#10 2021-11-19 12:28:28 -05:00
Implement CRC
morgan opened issue morgan/esp32-lora#9 2021-11-19 02:28:25 -05:00
Issue while reading in implicit header mode
morgan closed issue morgan/esp32-dual-lora#1 2021-11-18 13:22:15 -05:00
Add breakout header
morgan commented on issue morgan/esp32-dual-lora#1 2021-11-18 13:22:15 -05:00
Add breakout header

Six pin header added with 3v3/gnd and 4 GPIOs

morgan pushed to development at morgan/esp32-dual-lora 2021-11-18 13:21:22 -05:00
8f01c963ec broke out last available gpios
morgan opened issue morgan/esp32-dual-lora#3 2021-11-18 13:20:18 -05:00
Add SOICBite programming interface
morgan opened issue morgan/esp32-lora#8 2021-11-17 22:42:02 -05:00
Implement Channel H o p p i n g
morgan opened issue morgan/esp32-lora#7 2021-11-17 22:41:46 -05:00
Implement RSSI
morgan opened issue morgan/esp32-lora#6 2021-11-17 22:41:27 -05:00
set_lna results in different values depending on device
morgan opened issue morgan/esp32-lora#5 2021-11-17 22:40:26 -05:00
Reduce all DIO interrupt handling to single ISR/task pair
morgan pushed to multidev-wip at morgan/esp32-lora 2021-11-17 22:34:43 -05:00
db9b74ec76 renamed idle to standby to better reflect datasheet
14cd5df1e3 implement single RX, still needs timeout handling
8f07873624 reimplementing semephore and bus locking seems to have helped overall stability, particularly on first init
dc78e9b137 remove assert(REG_VERSION) in favor of returning error so application recovery is possible
Compare 4 commits »