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Author SHA1 Message Date
Morgan 'ARR\!' Allen
ca8954e5fd Merge branch 'development' of git.oit.cloud:morgan/RE-TM245P into development 2024-02-20 08:50:44 -08:00
Morgan 'ARR\!' Allen
dbc62e4e4f note on bus_splitter 2024-02-20 08:50:32 -08:00
Morgan 'ARR\!' Allen
7f9592483d kicad project files for bus splitter 2024-02-20 08:46:47 -08:00
Morgan 'ARR\!' Allen
04ba4d86cc slight update to README 2024-02-20 08:46:07 -08:00
4 changed files with 8632 additions and 1 deletions

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@ -23,6 +23,16 @@ Communication is done over the VP230 CAN Transceiver, though it doesn't look to
Instead the STM32 USART1 is connected so it's doing Syncronous UART over CAN. So it's really
just using the VP230 for differential signaling.
# Reading
# What's Done
* Schematic of STM32 <-> VP230 (CAN Bus)
* Verified STM32 read protection is in place :(
# Bus Splitter
The `bus_splitter` directory contains a KiCAD project to attempt reverse engineering the protocol
'monkey-in-the-middle' style. It contains two CAN bus transceivers, with the UART in between them
being passed to a set of header pins. The idea being the RX/TX pins can be attached to an
external microcontroller, allowing message to be inspected, modified and/or passed through as is.
# Further Reading
https://www.eevblog.com/forum/manufacture/neoden-tm245p-teardown-and-upgrade/

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@ -0,0 +1,420 @@
{
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"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
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"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
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"fab_text_upright": false,
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"other_text_size_h": 1.0,
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"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.15,
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"silk_text_size_h": 1.0,
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"meta": {
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"rule_severities": {
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"items_not_allowed": "error",
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"missing_courtyard": "ignore",
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"use_height_for_length_calcs": true
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"zones_allow_external_fillets": false,
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},
"layer_presets": []
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"boards": [],
"cvpcb": {
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"erc": {
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"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
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},
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},
"net_settings": {
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"clearance": 0.2,
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"diff_pair_width": 0.2,
"line_style": 0,
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"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
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"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
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},
"net_colors": null
},
"pcbnew": {
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"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
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},
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},
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"meta": {
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},
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"ngspice": {
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"meta": {
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},
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"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
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},
"sheets": [
[
"e63e39d7-6ac0-4ffd-8aa3-1841a4541b55",
""
]
],
"text_variables": {}
}

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